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Application-specific instruction set processor
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<h2 id="examples">Examples</h2> <p><a href="/facts/RISC-V/pUSKDat1">RISC-V Instruction Set Architecture</a> (ISA) provides minimum base instruction sets that can be extended with additional application-specific instructions.<a class="footnote-ref" id="fnref:5" href="#fn:5"><sup>5</sup></a> The base instruction sets provide simplified control flow, memory and arithmetic operations on registers. Its modular design allows the base instructions to be extended for standard application-specific operations such as integer multiplication/division (M), single-precision floating point (F), or bit manipulation (B). For the non-standard instruction extensions, encoding space of the ISA is divided into three parts: <i>standard, reserverd,</i> and <i>custom.</i> The <i>custom</i> encoding space is used for vendor-specific extensions. </p> <h2 id="see-also">See also</h2> <ul><li><a href="/facts/Application-specific_integrated_circuit/YGUXpX50">Application-specific integrated circuit</a></li> <li><a href="/facts/System_on_Chip/1RVvVe6N">System on Chip</a></li> <li><a href="/facts/Digital_signal_processor/YuBXweos">Digital signal processor</a></li></ul> <h2 id="literature">Literature</h2> <ul><li>Dake Liu (2008). <i>Embedded DSP Processor Design: Application Specific Instruction Set Processors</i>. MA: Elsevier Mogan Kaufmann. <a href="/facts/ISBN_(identifier)/15AdSPa9">ISBN</a> 978-0-12-374123-3.</li> <li>Oliver Schliebusch; Heinrich Meyr; Rainer Leupers (2007). <i>Optimized ASIP Synthesis from Architecture Description Language Models</i>. Dordrecht: Springer. <a href="/facts/ISBN_(identifier)/15AdSPa9">ISBN</a> 978-1-4020-5685-7.</li> <li>Paolo Ienne, Rainer Leupers (eds.) (2006). <i>Customizable Embedded Processors</i>. San Mateo, CA: Morgan Kaufmann. <a href="/facts/ISBN_(identifier)/15AdSPa9">ISBN</a> 978-0-12-369526-0. {{cite book}}: |author= has generic name (help)</li> <li>Matthias Gries, Kurt Keutzer (eds.) (2005). <i>Building ASIPs: The Mescal Methodology</i>. New York: Springer. <a href="/facts/ISBN_(identifier)/15AdSPa9">ISBN</a> 978-0-387-26057-0. {{cite book}}: |author= has generic name (help)</li></ul> <h2 id="external-links">External links</h2> <ul><li><a href="http://tce.cs.tut.fi">TTA-Based Codesign Environment (TCE), an open source (MIT licensed) toolset for design of application specific TTA processors.</a></li></ul> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>Jain, M.K.; Balakrishnan, M.; Kumar, A. (2001). "ASIP design methodologies: Survey and issues". VLSI Design 2001. Fourteenth International Conference on VLSI Design. Bangalore, India: IEEE Comput. Soc. pp. 76–81. doi:10.1109/ICVD.2001.902643. ISBN 978-0-7695-0831-3. S2CID 14053636. <a href="978-0-7695-0831-3" target="_blank">978-0-7695-0831-3</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>Shahabuddin, Shahriar et al., "Design of a transport triggered vector processor for turbo decoding", Springer Journal of Analog Integrated Circuits and Signal Processing, March 2014. <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li> <li id="fn:3"><p>Hautala, Ilkka, et al. "Programmable Low-Power Multicore Coprocessor Architecture for HEVC/H.265 In-Loop Filtering" in IEEE Transactions on Circuits and Systems for Video Technology, November 2014 <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li> <li id="fn:4"><p>Masarík, UML in design of ASIP, IFAC Proceedings Volumes 39(17):209-214, September 2006 <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li> <li id="fn:5"><p>Krste, CALIFORNIA UNIV BERKELEY DEPT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES Waterman, Andrew Lee, Yunsup Patterson, David A Asanovi (May 6, 2014). The RISC-V Instruction Set Manual. Volume 1: User-Level ISA, Version 2.0. OCLC 913589579.{{cite book}}: CS1 maint: multiple names: authors list (link) <a href="http://worldcat.org/oclc/913589579" target="_blank">http://worldcat.org/oclc/913589579</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></p></li> </ol>