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Architecture Design and Assessment System
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<h2 id="simulation-model">Simulation Model</h2> <p>An ADAS model consisted of nodes connected by directed arcs. </p><p>For abstract simulation a node represents a <a href="/facts/Process_(systems_engineering)/gFwRmkDp">process (systems engineering)</a> in the system that is being modeled. The readiness for execution or firing of this process requires that: its inputs are satisfied, space is available for its outputs, and its shared resource/hardware is available. During execution the node consumes its inputs, uses the resource for the prescribed duration, then produces its outputs. </p><p>The inputs and outputs of a process are represented by discrete tokens. These tokens flow along the arcs in the graph. If the maximum arc size is greater than one, then an arc would represent a buffer between system processes. </p><p>To refine the model of the system, a subgraph could be placed below the node to refine the behavior of that process. </p><p>Physical and behavioral properties were attached to nodes and arcs in the form of attributes. The attribute definition language allowed the computation of attributes from ancestor attributes and global values. </p> <h2 id="further-reading">Further reading</h2> <ul><li><a href="http://portal.acm.org/citation.cfm?id=317825.317921">An Architecture Design and Assessment System for Software/Hardware Codesign, Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985</a></li> <li><a href="http://www.informatik.uni-hamburg.de/TGI/pnbib/z/zobrist_g_w1.html">The Modified Computational Graph and its Usage in Concurrent System Design and Analysis, Proc. of the Fifth Int. Conf. on Systems Engineering, pages 385-388. New York: IEEE, 1987</a></li> <li><a href="https://ieeexplore.ieee.org/document/117945/">The Modelling of a Spaceflight Optical Disk Recorder Controller Using the Architecture Design and Assessment System, IEEE Southeast Con, Apr 1990</a></li> <li><a href="http://ieeexplore.ieee.org/Xplore/login.jsp?url=/iel2/145/5237/00203146.pdf?arnumber=203146">Application of Structured Analysis to a Telerobotic System, IEEE International Conference on System Engineering, Aug 1990</a>[<i>dead link</i>]</li> <li><a href="https://web.archive.org/web/20110517182337/http://www.aiaa.org/content.cfm?pageid=406&gTable=mtgpaper&gID=63108">Multiprocessor Performance Modeling with ADAS, AIAA Computers in Aerospace Conference, 7th, Monterey, CA, Oct 3-5, 1989</a></li> <li><a href="https://web.archive.org/web/20110517182353/http://www.aiaa.org/content.cfm?pageid=406&gTable=mtgpaper&gID=63109">Modeling and Analysis of Multiprocessor Architectures, AIAA-1989-3014</a></li> <li><a href="http://doi.ieeecomputersociety.org/10.1109/2.25383">The Test Engineer's Assistant: A Support Environment for Hardware Design for Testability, IEEE Computer Apr. 1989</a></li> <li>Integration of Tools for the Design and Assessment of High-Performance, Highly Reliable Computing System (DAHPHRS) Phase 1, NASA Contract NAS1-17964, May 1992, page 141 <a href="https://ntrs.nasa.gov/archive/nasa/casi.ntrs.nasa.gov/19920019342_1992019342.pdf">https://ntrs.nasa.gov/archive/nasa/casi.ntrs.nasa.gov/19920019342_1992019342.pdf</a></li> <li><a href="https://doi.org/10.1007%2FBF00935213">CSP-based object-oriented description and simulation of a reconfigurable adaptive beamforming architecture using the OODRA workbench, The Journal of VLSI Signal Processing, Nov 1990</a></li> <li><a href="https://ntrs.nasa.gov/search.jsp?R=36107&id=1&qs=Ne%3D41%26N%3D4294814590%26Ns%3DArchiveName%257C0">Aircraft design for mission performance using nonlinear multiobjective optimization methods, Journal of Aircraft (ISSN 0021-8669), vol. 27, Dec. 1990</a></li> <li><a href="http://portal.acm.org/citation.cfm?doid=210330.210333">Parallelism in Sequential Multiprocessor Simulation Models: a Case Study, ACM Transactions on Modeling and Computer Simulation, Apr. 1995</a></li> <li>The Practice of Prolog: a Prolog-based VLSI editor, Leon Sterling, 1990, <a href="/facts/ISBN_(identifier)/15AdSPa9">ISBN</a> 0-262-19301-9</li> <li><a href="https://ieeexplore.ieee.org/document/230671/">Design Automation Technology for Codesign: Status and Directions, 1992 IEEE International Symposium on Circuits and Systems</a></li> <li><a href="https://ieeexplore.ieee.org/document/165823/">Aladdin Software Support, Proceedings of the IEEE 1991 National Aerospace and Electronics Conference</a></li> <li>Performance Analysis of a Large-Grain Dataflow Scheduling Paradigm, NASA Langley, June 1993, page 8 <a href="https://ntrs.nasa.gov/archive/nasa/casi.ntrs.nasa.gov/19930023024_1993023024.pdf">https://ntrs.nasa.gov/archive/nasa/casi.ntrs.nasa.gov/19930023024_1993023024.pdf</a></li> <li><a href="https://ieeexplore.ieee.org/document/111315/">Automated Fault Tolerance Evaluator for System Design, Simulation, and Analysis, Proceedings., IEEE/AIAA/NASA 9th Digital Avionics Systems Conference, 1990</a></li> <li>Virtual Prototyping, Digital Signal Processing Systems, 1998 Lockheed Martin Technology Symposium, slide 7 <a href="https://web.archive.org/web/20110904153705/http://www.atl.lmco.com/projects/csim/vp4C.pdf">https://web.archive.org/web/20110904153705/http://www.atl.lmco.com/projects/csim/vp4C.pdf</a></li></ul> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>G.A. Frank, D.L. Franke, and W.F. Ingogly, "An Architecture Design and Assessment System,"VLSI Design, Vol. 6, No. 8, Aug. 1985, pp. 30-50 <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> </ol>