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VerilogCSP
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<h2 id="external-links">External links</h2> <ul><li><a href="https://web.archive.org/web/20060906072827/http://jungfrau.usc.edu/new/research/current/verilogcsp/index.html">VerilogCSP Homepage</a></li></ul> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>Saifhashemi, Arash; Peter Beerel (2005). "High Level Modeling of Channel-Based Asynchronous Circuits Using Verilog". In Jan Broenink; Herman Roebbers; Johan Sunter; Peter Welch; David Wood (eds.). Communicating Process Architectures 2005. IOS Press. p. 275. <a href="http://www.wotug.org/paperdb/send_file.php?num=148" target="_blank">http://www.wotug.org/paperdb/send_file.php?num=148</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> </ol>