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NOR gate
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<h2 id="symbols">Symbols</h2> <p>There are three symbols for NOR gates: the American (ANSI or 'military') symbol and the IEC ('European' or 'rectangular') symbol, as well as the deprecated <a href="/facts/DIN/BGemsWax">DIN</a> symbol. For more information see <a href="/facts/Logic_gate/RHLulvKI">Logic Gate Symbols</a>. The ANSI symbol for the NOR gate is a standard OR gate with an inversion bubble connected. The bubble indicates that the function of the or gate has been inverted. </p> <table><tbody><tr><td></td><td></td><td></td></tr><tr><td><i>MIL/ANSI Symbol</i> </td><td><i>IEC Symbol</i> </td><td><i>DIN Symbol</i></td></tr></tbody></table> <h2 id="hardware-description-and-pinout">Hardware description and pinout</h2> <p>NOR Gates are basic logic gates, and as such they are recognised in <a href="/facts/Transistor%25E2%2580%2593transistor_logic/z4bvHotl">TTL</a> and <a href="/facts/CMOS/NJIWYgBl">CMOS</a> <a href="/facts/Integrated_circuit/fjn6vg7C">ICs</a>. The standard, <a href="/facts/4000_series/x505SAg7">4000 series</a>, CMOS IC is the 4001, which includes four independent, two-input, NOR gates. The pinout diagram is as follows: </p> <table><tbody><tr><td></td><td> 1 Input A1 2 Input B1 3 Output Q1 4 Output Q2 5 Input B2 6 Input A2 7 Vss 8 Input A3 9 Input B3 10 Output Q3 11 Output Q4 12 Input B4 13 Input A4 14 Vdd</td></tr></tbody></table> <h3>Availability</h3> <p>These devices are available from most semiconductor manufacturers such as <a href="/facts/Fairchild_Semiconductor/TUD8v4P0">Fairchild Semiconductor</a>, <a href="/facts/Philips/Xp4uczGg">Philips</a> or <a href="/facts/Texas_Instruments/88NUhuHF">Texas Instruments</a>. These are usually available in both through-hole <a href="/facts/Dual_in-line_package/Qgu6Jave">DIP</a> and <a href="/facts/Small-outline_integrated_circuit/bu2NdrhV">SOIC</a> format. Datasheets are readily available in most <a href="/facts/Datasheet/U4PhwRJM">datasheet databases</a>. </p><p>In the popular CMOS and TTL <a href="/facts/Logic_families/QlEgIecX">logic families</a>, NOR gates with up to 8 inputs are available: </p> <ul><li><a href="/facts/CMOS/NJIWYgBl">CMOS</a> <ul><li>4001: Quad 2-input NOR gate</li> <li>4025: Triple 3-input NOR gate</li> <li>4002: Dual 4-input NOR gate</li> <li>4078: Single 8-input NOR gate</li></ul></li> <li><a href="/facts/Transistor-transistor_logic/z4bvHotl">TTL</a> <ul><li>7402: Quad 2-input NOR gate</li> <li>7427: Triple 3-input NOR gate</li> <li>7425: Dual 4-input NOR gate (with strobe, obsolete)</li> <li>74260: Dual 5-Input NOR Gate</li> <li>744078: Single 8-input NOR Gate</li></ul></li></ul> <p>In the older <a href="/facts/Resistor%25E2%2580%2593transistor_logic/V9JGuspy">RTL</a> and <a href="/facts/Emitter-coupled_logic/wAN1uEgH">ECL</a> families, NOR gates were efficient and most commonly used. </p> <h2 id="implementations">Implementations</h2> <table><tbody><tr><td></td><td></td><td></td></tr></tbody></table> <p>The left diagram above show the construction of a 2-input NOR gate using <a href="/facts/NMOS_logic/6hup3T21">NMOS logic</a> circuitry. If either of the inputs is high, the corresponding N-channel <a href="/facts/MOSFET/eTDJT2Km">MOSFET</a> is turned on and the output is pulled low; otherwise the output is pulled high through the <a href="/facts/Pull-up_resistor/zeEjjrqk">pull-up resistor</a>. In the CMOS implementation on the right, the function of the pull-up resistor is implemented by the two p-type transistors in series on the top. </p> <p>In CMOS, NOR gates are less efficient than <a href="/facts/NAND_gate/g6FUuhJT">NAND gates</a>. This is due to the faster charge mobility in n-MOSFETs compared to p-MOSFETs, so that the parallel connection of two p-MOSFETs realised in the NAND gate is more favourable than their series connection in the NOR gate. For this reason, NAND gates are generally preferred over NOR gates in CMOS circuits.<a class="footnote-ref" id="fnref:1" href="#fn:1"><sup>1</sup></a> </p> <h2 id="functional-completeness">Functional completeness</h2> <p class="note">Main article: <a href="/facts/NOR_logic/GhHdKb4q">NOR logic</a></p> <p>The NOR gate has the property of <a href="/facts/Functional_completeness/ncyHAsHH">functional completeness</a>, which it shares with the NAND gate. That is, any other logic function (AND, OR, etc.) can be implemented using only NOR gates.<a class="footnote-ref" id="fnref:2" href="#fn:2"><sup>2</sup></a> An entire processor can be created using NOR gates alone. The original <a href="/facts/Apollo_Guidance_Computer/xGxHlrXY">Apollo Guidance Computer</a> used 4,100 integrated circuits (IC), each one containing only two 3-input NOR gates.<a class="footnote-ref" id="fnref:3" href="#fn:3"><sup>3</sup></a> </p><p> As NAND gates are also functionally complete, if no specific NOR gates are available, one can be made from <a href="/facts/NAND_gate/g6FUuhJT">NAND</a> gates using <a href="/facts/NAND_logic/ye1XC5Ac">NAND logic</a>.<a class="footnote-ref" id="fnref:4" href="#fn:4"><sup>4</sup></a> </p> <table><tbody><tr><th>Desired gate</th><th>NAND Construction</th></tr><tr><td></td><td></td></tr></tbody></table> <h2 id="see-also">See also</h2> <ul><li><a href="/facts/AND_gate/tVKQD0w1">AND gate</a></li> <li><a href="/facts/OR_gate/ox2lHgIM">OR gate</a></li> <li><a href="/facts/Inverter_(logic_gate)/pGk3qGTI">NOT gate</a></li> <li><a href="/facts/NAND_gate/g6FUuhJT">NAND gate</a></li> <li><a href="/facts/XOR_gate/WSfdqTcA">XOR gate</a></li> <li><a href="/facts/XNOR_gate/LW793PwY">XNOR gate</a></li> <li><a href="/facts/NAND_logic/ye1XC5Ac">NAND logic</a></li> <li><a href="/facts/Boolean_algebra_(logic)/VkCToAmg">Boolean algebra (logic)</a></li> <li><a href="/facts/Flash_memory/Cn8JsStx">Flash memory</a></li></ul> Wikimedia Commons has media related to NOR gates. <h2 id="references">References</h2> <ol> <li id="fn:1"><p>Smith, J.S. "Digital circuits, sizing, output impedance, rise and fall time" (PDF). Archived from the original (PDF) on 2007-07-06. <a href="https://web.archive.org/web/20070706145946/https://inst.eecs.berkeley.edu/~ee105/sp04/handouts/lectures/Lecture18.pdf" target="_blank">https://web.archive.org/web/20070706145946/https://inst.eecs.berkeley.edu/~ee105/sp04/handouts/lectures/Lecture18.pdf</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>Mano, M. Morris and Charles R. Kime. Logic and Computer Design Fundamentals, Third Edition. Prentice Hall, 2004. p. 73. <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li> <li id="fn:3"><p>Whipple, Walt (2019). First-Hand:Hacking Apollo's Guidance Computer. Engineering and Technology History Wiki. <a href="https://ethw.org/First-Hand:Hacking_Apollo%27s_Guidance_Computer" target="_blank">https://ethw.org/First-Hand:Hacking_Apollo%27s_Guidance_Computer</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li> <li id="fn:4"><p>Mano, M. Morris and Charles R. Kime. Logic and Computer Design Fundamentals, Third Edition. Prentice Hall, 2004. p. 73. <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li> </ol>