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<h2 id="instruction-set">Instruction set</h2> <p>The instructions are almost identical to the standard ARM formats, except that conditional execution has been removed, and the bits reassigned to expand all the register specifiers to 5 bits.<a class="footnote-ref" id="fnref:6" href="#fn:6"><sup>6</sup></a><a class="footnote-ref" id="fnref:7" href="#fn:7"><sup>7</sup></a> Likewise, the immediate format is 9 bits rotated by a 5-bit amount (rather than 8 bit rotated by 4), the load/store offset sizes are 14 bits for byte/word and 10 bits for signed byte or half-word. Conditional moves are provided by encoding the condition in the (unused by ARM) second source register field Rn for MOV and MVN instructions. </p> Unicore32 instruction set overview<a class="footnote-ref" id="fnref:8" href="#fn:8"><sup>8</sup></a><table><tbody><tr><th>31</th><th>30</th><th>29</th><th>28</th><th>27</th><th>26</th><th>25</th><th>24</th><th>23</th><th>22</th><th>21</th><th>20</th><th>19</th><th>18</th><th>17</th><th>16</th><th>15</th><th>14</th><th>13</th><th>12</th><th>11</th><th>10</th><th>9</th><th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th><th>Description</th></tr><tr><td>0</td><td>0</td><td>0</td><td colspan="4"><i>opcode</i></td><td>S</td><td colspan="5">Rn</td><td colspan="5">Rd</td><td colspan="5">shift</td><td>0</td><td colspan="2">Sh</td><td>0</td><td colspan="5">Rm</td><td>ALU operation, Rd = Rn <i>op</i> Rm <i>shift</i> #shift</td></tr><tr><td>0</td><td>0</td><td>0</td><td colspan="4"><i>opcode</i></td><td>S</td><td colspan="5">Rn</td><td colspan="5">Rd</td><td colspan="5">Rs</td><td>0</td><td colspan="2">Sh</td><td>1</td><td colspan="5">Rm</td><td>ALU operation, Rd = Rn <i>op</i> Rm <i>shift</i> Rs</td></tr><tr><td>0</td><td>0</td><td>1</td><td colspan="4"><i>opcode</i></td><td>S</td><td colspan="5">Rn</td><td colspan="5">Rd</td><td colspan="5">shift</td><td colspan="9">imm9</td><td>ALU operation, Rd = Rn <i>op</i> #imm9 ROTL #shift</td></tr><tr><td>0</td><td>1</td><td>0</td><td>P</td><td>U</td><td>B</td><td>W</td><td>L</td><td colspan="5">Rn</td><td colspan="5">Rd</td><td colspan="5">shift</td><td>0</td><td colspan="2">Sh</td><td>0</td><td colspan="5">Rm</td><td>Load/store Rd to address Rn ± Rm <i>shift</i> #shift</td></tr><tr><td>0</td><td>1</td><td>1</td><td>P</td><td>U</td><td>B</td><td>W</td><td>L</td><td colspan="5">Rn</td><td colspan="5">Rd</td><td colspan="14">offset14</td><td>Load/store Rd to address Rn ± offset14</td></tr><tr><td>1</td><td>0</td><td>0</td><td>P</td><td>U</td><td>S</td><td>W</td><td>L</td><td colspan="5">Rn</td><td colspan="10">Bitmap high</td><td>0</td><td>0</td><td>H</td><td colspan="6">Bitmap low</td><td>Load/store multiple registers</td></tr><tr><td>1</td><td>0</td><td>1</td><td colspan="4"><i>cond</i></td><td>L</td><td colspan="24">offset24</td><td>Branch (and link) if condition true</td></tr><tr><td>1</td><td>1</td><td>0</td><td colspan="29"></td><td>Coprocessor (FPU) instructions</td></tr><tr><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td colspan="24">Trap number</td><td>Software interrupt</td></tr><tr><td colspan="33"></td></tr><tr><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>A</td><td>S</td><td colspan="5">Rn</td><td colspan="5">Rd</td><td colspan="5">Rs</td><td>1</td><td>0</td><td>0</td><td>1</td><td colspan="5">Rm</td><td>Multiply, Rd = Rm * Rs (+ Rn)</td></tr><tr><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>L</td><td colspan="5">11111</td><td colspan="5">11111</td><td colspan="5">00000</td><td>1</td><td>0</td><td>0</td><td>1</td><td colspan="5">Rm</td><td>Branch and exchange (BX, BLX)</td></tr><tr><td>0</td><td>1</td><td>0</td><td>P</td><td>U</td><td>0</td><td>W</td><td>L</td><td colspan="5">Rn</td><td colspan="5">Rd</td><td colspan="5">00000</td><td>1</td><td>S</td><td>H</td><td>1</td><td colspan="5">Rm</td><td>Load/store Rd to address Rn ± Rm (16-bit)</td></tr><tr><td>0</td><td>1</td><td>0</td><td>P</td><td>U</td><td>1</td><td>W</td><td>L</td><td colspan="5">Rn</td><td colspan="5">Rd</td><td colspan="5">imm_hi</td><td>1</td><td>S</td><td>H</td><td>1</td><td colspan="5">imm_lo</td><td>Load/store Rd to address Rn ± #imm10 (16-bit)</td></tr></tbody></table> <p>The meaning of various flag bits (such as S=1 enables setting the condition codes) is identical to the ARM instruction set. The load/store multiple instruction can only access half of the register set, depending on the H bit. If H=0, the 16 bits indicate R0–R15; if H=1, R16–R31. </p> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>"Introduction to MPRC". Microprocessor Research and Develop Center, Peking University. <a href="http://mprc.pku.cn/eng/intro.html" target="_blank">http://mprc.pku.cn/eng/intro.html</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>Xu Cheng; Xiaoyin Wang; Junlin Lu; Jiangfang Yi; Dong Tong; Xuetao Guan; Feng Liu; Xianhua Liu; Chun Yang; Yi Feng (March 2010), "Research Progress of UniCore CPUs and PKUnity SoCs" (PDF), Journal of Computer Science and Technology, 25 (2): 200–213, doi:10.1007/s11390-010-9317-1, S2CID 7083916, retrieved 2012-07-11 <a href="http://mprc.pku.edu.cn/~guanxuetao/publications/2010-JCST-CX.pdf" target="_blank">http://mprc.pku.edu.cn/~guanxuetao/publications/2010-JCST-CX.pdf</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li> <li id="fn:3"><p>Bergmann, Arnd (2012-07-09). "Re: [PATCH 00/36] AArch64 Linux kernel port". linux-kernel (Mailing list). Retrieved 2012-07-11. Another interesting example is unicore32, which actually shares more code with arch/arm than the proposed arch/aarch64 does. I think the unicore32 code base would benefit from being merged back into arch/arm as a third instruction set, but the additional maintenance cost for everyone working on ARM makes that unrealistic. <a href="https://marc.info/?l=linux-kernel&m=134184818409286" target="_blank">https://marc.info/?l=linux-kernel&m=134184818409286</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li> <li id="fn:4"><p>"Merge window closed - 2.6.39-rc1 out". Linus Torvalds. <a href="https://lkml.org/lkml/2011/3/29/351" target="_blank">https://lkml.org/lkml/2011/3/29/351</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li> <li id="fn:5"><p>"remove unicore32 support". Mike Rapoport. <a href="https://lkml.org/lkml/2020/8/3/232" target="_blank">https://lkml.org/lkml/2020/8/3/232</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></p></li> <li id="fn:6"><p>Hsu-Hung Chiang; Huang-Jia Cheng; Yuan-Shin Hwan (2012-02-25), "Doubling the Number of Registers on ARM Processors" (PDF), 16th Workshop on Interaction between Compilers and Computer Architectures (INTERACT), pp. 1–8, doi:10.1109/INTERACT.2012.6339620, ISBN 978-1-4673-2613-1, S2CID 6832041 <a href="978-1-4673-2613-1" target="_blank">978-1-4673-2613-1</a> <a href="#fnref:6" class="footnote-back-ref">↩</a></p></li> <li id="fn:7"><p>Unicore processor simulator source code. Instruction formats are in decode.c, disassembly in interpret.c, and emulation in instEx.c. <a href="https://code.google.com/p/minic/source/browse/trunk/simulator/" target="_blank">https://code.google.com/p/minic/source/browse/trunk/simulator/</a> <a href="#fnref:7" class="footnote-back-ref">↩</a></p></li> <li id="fn:8"><p>QEMU Unicore32 emulator source code <a href="https://github.com/qemu/qemu/blob/HEAD/target/unicore32/translate.c" target="_blank">https://github.com/qemu/qemu/blob/HEAD/target/unicore32/translate.c</a> <a href="#fnref:8" class="footnote-back-ref">↩</a></p></li> </ol>