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Permute instruction
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<h2 id="occurrences-of-permute-instructions">Occurrences of permute instructions</h2> <p>Permute instructions occur in both <a href="/facts/Scalar_processor/Rwma07cc">scalar processors</a> as well as <a href="/facts/Vector_processors/nYAsIKT0">vector processing</a> engines as well as <a href="/facts/Graphics_processing_unit/PTK1RQVp">GPUs</a>. In vector instruction sets they are typically named "Register Gather/Scatter" operations such as in <a href="/facts/RISC-V/pUSKDat1">RISC-V</a> vectors,<a class="footnote-ref" id="fnref:2" href="#fn:2"><sup>2</sup></a> and take Vectors as input for both source elements and source array, and output another Vector. </p><p>In scalar instruction sets the scalar registers are broken down into smaller sections (unpacked, <a href="/facts/SIMD/gQHWQSpo">SIMD</a> style) where the fragments are then used as array sources. The (small, partial) results are then concatenated (packed) back into the scalar register as the result. </p><p>Some ISAs, particularly for <a href="/facts/Cryptographic/e94PEVau">cryptographic</a> applications, even have <i>bit-level</i> permute operations, such as bdep (bit deposit) in RISC-V bitmanip;<a class="footnote-ref" id="fnref:3" href="#fn:3"><sup>3</sup></a> in the <a href="/facts/Power_ISA/GLy1WS0m">Power ISA</a> it is known as bpermd and has been included for several decades, and is still in the Power ISA v.3.0 B spec.<a class="footnote-ref" id="fnref:4" href="#fn:4"><sup>4</sup></a> </p><p>Also in some non-vector ISAs, due to there sometimes being insufficient space in the one source input register to specify the permutation source array in full (particularly if the operation involves bit-level permutation), will include partial reordering instructions. Examples include VSHUFF32x4 from <a href="/facts/AVX-512/2KpGqI8t">AVX-512</a>. </p><p>Permute operations in different forms are surprisingly common, occurring in <a href="/facts/AltiVec/Vn1DY71U">AltiVec</a>, <a href="/facts/Power_ISA/GLy1WS0m">Power ISA</a>, <a href="/facts/PowerPC_G4/llrBTyVn">PowerPC G4</a>, <a href="/facts/AVX-512/2KpGqI8t">AVX-512</a>, <a href="/facts/Scalable_Vector_Extension/bauXRos7">SVE2</a>,<a class="footnote-ref" id="fnref:5" href="#fn:5"><sup>5</sup></a> vector processors, and <a href="/facts/Graphics_processing_unit/PTK1RQVp">GPUs</a>. They are sufficiently important that <a href="/facts/LLVM/nPmcspQN">LLVM</a> added the shufflevector<a class="footnote-ref" id="fnref:6" href="#fn:6"><sup>6</sup></a> intrinsic and <a href="/facts/GNU_Compiler_Collection/t07jh01k">GCC</a> added the __builtin_shuffle intrinsic.<a class="footnote-ref" id="fnref:7" href="#fn:7"><sup>7</sup></a> GCC's intrinsic matches the functionality of <a href="/facts/OpenCL/ns8y6np7">OpenCL</a>'s shuffle intrinsics.<a class="footnote-ref" id="fnref:8" href="#fn:8"><sup>8</sup></a> Note that all of these, mathematically, are not permutations because duplicates can occur in the output. </p> <h2 id="see-also">See also</h2> <ul><li><a href="/facts/Kepler_(microarchitecture)/NU6RAHIQ">Kepler (microarchitecture) § Shuffle Instructions</a></li> <li><a href="/facts/GeForce_700_series/KoLvJeCt">GeForce 700 series § New shuffle Instructions</a></li></ul> <h2 id="external-links">External links</h2> <ul><li><a href="https://www.felixcloutier.com/x86/vshuff32x4:vshuff64x2:vshufi32x4:vshufi64x2">Unofficial convenient list of AVX-512 shuffle instructions</a></li> <li><a href="https://software.intel.com/sites/default/files/managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf">Official Intel AVX-512 ISA Manual</a></li> <li><a href="https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/coding-for-neon---part-5-rearranging-vectors">ARM NEON tutorial on data rearrangement</a></li></ul> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>Intel® 64 and IA-32 architectures software developer's manual combined volumes: 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4 (PDF). Intel. June 2021. p. 5-356 Vol. 2C. <a href="https://software.intel.com/content/dam/develop/external/us/en/documents-tps/325462-sdm-vol-1-2abcd-3abcd.pdf" target="_blank">https://software.intel.com/content/dam/develop/external/us/en/documents-tps/325462-sdm-vol-1-2abcd-3abcd.pdf</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>"RISC-V "V" Vector Extension – 16.4. Vector Register Gather Instructions". GitHub – riscv/riscv-v-spec. Retrieved 2021-07-10. <a href="https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-register-gather-instructions" target="_blank">https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-register-gather-instructions</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li> <li id="fn:3"><p>"riscv/riscv-bitmanip". GitHub. Retrieved 2021-07-10. <a href="https://github.com/riscv/riscv-bitmanip" target="_blank">https://github.com/riscv/riscv-bitmanip</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li> <li id="fn:4"><p>"Power ISA Version 3.0 B". Power.org. 2017-03-27. Retrieved 2019-08-11. <a href="https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0" target="_blank">https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li> <li id="fn:5"><p>ARM HPC, SVE2 Extension summary, p32 <a href="https://indico.ph.ed.ac.uk/event/69/contributions/892/attachments/734/910/Arm_Exascale.pdf" target="_blank">https://indico.ph.ed.ac.uk/event/69/contributions/892/attachments/734/910/Arm_Exascale.pdf</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></p></li> <li id="fn:6"><p>"LLVM 13 documentation: shufflevector". LLVM Language Reference Manual. Retrieved 2021-07-10. <a href="https://llvm.org/docs/LangRef.html#shufflevector-instruction" target="_blank">https://llvm.org/docs/LangRef.html#shufflevector-instruction</a> <a href="#fnref:6" class="footnote-back-ref">↩</a></p></li> <li id="fn:7"><p>"Vector Extensions (Using the GNU Compiler Collection (GCC))". GCC, the GNU Compiler Collection - GNU Project - Free Software Foundation (FSF). Retrieved 2021-07-10. <a href="https://gcc.gnu.org/onlinedocs/gcc/Vector-Extensions.html" target="_blank">https://gcc.gnu.org/onlinedocs/gcc/Vector-Extensions.html</a> <a href="#fnref:7" class="footnote-back-ref">↩</a></p></li> <li id="fn:8"><p>"OpenCL Specification: shuffle, shuffle2". The Khronos Group Inc. Retrieved 2021-07-10. <a href="https://www.khronos.org/registry/OpenCL/sdk/2.1/docs/man/xhtml/shuffle.html" target="_blank">https://www.khronos.org/registry/OpenCL/sdk/2.1/docs/man/xhtml/shuffle.html</a> <a href="#fnref:8" class="footnote-back-ref">↩</a></p></li> </ol>