2 nm process

<h2 id="background">Background</h2>
By 2018, a number of transistor architectures had been proposed for the eventual replacement of <a href="/facts/FinFET/xox63kP7">FinFET</a>, most of which were based on the concept of <a href="/facts/GAAFET/YTeIYBvc">GAAFET</a>:<a class="footnote-ref" id="fnref:8" href="#fn:8">8</a> horizontal and vertical nanowires, horizontal nanosheet transistors<a class="footnote-ref" id="fnref:9" href="#fn:9">9</a><a class="footnote-ref" id="fnref:10" href="#fn:10">10</a> (Samsung MBCFET, Intel Nanoribbon), vertical FET (VFET) and other vertical transistors,<a class="footnote-ref" id="fnref:11" href="#fn:11">11</a><a class="footnote-ref" id="fnref:12" href="#fn:12">12</a> complementary FET (CFET), stacked FET, several kinds of horizontal gate-all-around transistors such as nano-ring, hexagonal wire, square wire, and round wire gate-all-around transistors<a class="footnote-ref" id="fnref:13" href="#fn:13">13</a> and negative-capacitance FET (NC-FET) which uses drastically different materials.<a class="footnote-ref" id="fnref:14" href="#fn:14">14</a>
In late 2018, <a href="/facts/TSMC/B4BdojRk">TSMC</a> chairman Mark Liu predicted chip scaling would continue to 3 nm and 2 nm nodes;<a class="footnote-ref" id="fnref:15" href="#fn:15">15</a> however, as of 2019, other semiconductor specialists were undecided as to whether nodes beyond 3 nm could become viable.<a class="footnote-ref" id="fnref:16" href="#fn:16">16</a>[needs update] TSMC began research on 2 nm in 2019<a class="footnote-ref" id="fnref:17" href="#fn:17">17</a>—expecting to transition from FinFET to <a href="/facts/GAAFET/YTeIYBvc">GAAFET</a>.<a class="footnote-ref" id="fnref:18" href="#fn:18">18</a>[needs update] In July 2021, TSMC received governmental approval to build its 2 nm plant. In August 2020, it began building a research and development lab for 2 nm technology in <a href="/facts/Hsinchu/0lnateXN">Hsinchu</a>, expected to become partially operational by 2021.<a class="footnote-ref" id="fnref:19" href="#fn:19">19</a>[needs update] In September 2020, TSMC confirmed this and stated that it could also install production at <a href="/facts/Taichung/4dIPCQD7">Taichung</a> depending on demand.<a class="footnote-ref" id="fnref:20" href="#fn:20">20</a>[needs update] According to the Taiwan Economic Daily (2020), expectations were for high yield risk production in late 2023.<a class="footnote-ref" id="fnref:21" href="#fn:21">21</a><a class="footnote-ref" id="fnref:22" href="#fn:22">22</a>[needs update] According to <a href="/facts/Nikkei%2c_Inc./l5QYmEAC">Nikkei</a>, the company at that time expected to have been installing production equipment for 2 nm by 2023.<a class="footnote-ref" id="fnref:23" href="#fn:23">23</a>[needs update]
<a href="/facts/Intel/SMF0gJJX">Intel</a>'s 2019 roadmap scheduled potentially equivalent 3 nm and 2 nm nodes for 2025 and 2027, respectively, and in December 2019 announced plans for 1.4 nm production in 2029.<a class="footnote-ref" id="fnref:24" href="#fn:24">24</a>[needs update]
At the end of 2020, seventeen <a href="/facts/European_Union/6GYcR8qM">European Union</a> countries signed a joint declaration to develop their entire semiconductor industry, including developing process nodes as small as 2 nm, as well as designing and manufacturing custom processors, assigning up to €145 billion in funds.<a class="footnote-ref" id="fnref:25" href="#fn:25">25</a><a class="footnote-ref" id="fnref:26" href="#fn:26">26</a>[needs update]
In May 2021, <a href="/facts/IBM/QszA7nwd">IBM</a> announced it had produced chips with 2 nm-class GAAFET transistors using three silicon layer nanosheets with a gate length of 12 nm.<a class="footnote-ref" id="fnref:27" href="#fn:27">27</a><a class="footnote-ref" id="fnref:28" href="#fn:28">28</a><a class="footnote-ref" id="fnref:29" href="#fn:29">29</a>
In July 2021, Intel unveiled its process node roadmap from 2021 onwards. The company confirmed their 2 nm process node called "Intel 20A",<a class="footnote-ref" id="fnref:30" href="#fn:30">30</a> with "A" referring to an <a href="/facts/Angstrom/T5mjdd97">angstrom</a>, a unit equivalent to 0.1 nanometers.<a class="footnote-ref" id="fnref:31" href="#fn:31">31</a> At the same time, they introduced a new process node naming scheme that aligned their product names with similar designations from their main competitors.<a class="footnote-ref" id="fnref:32" href="#fn:32">32</a> Intel's 20A node was at that time projected to have been their first to move from FinFET to gate-all-around transistors (GAAFET); Intel's version was named '<a href="/facts/RibbonFET/YTeIYBvc">RibbonFET</a>'.<a class="footnote-ref" id="fnref:33" href="#fn:33">33</a> Their 2021 roadmap scheduled the Intel 20A node for volume production in 2024 and Intel 18A for 2025.<a class="footnote-ref" id="fnref:34" href="#fn:34">34</a><a class="footnote-ref" id="fnref:35" href="#fn:35">35</a>[needs update]
In October 2021, at Samsung Foundry Forum 2021, Samsung announced it would start mass production with its MBCFET (multi-bridge channel FET, Samsung's version of GAAFET) 2 nm process in 2025.<a class="footnote-ref" id="fnref:36" href="#fn:36">36</a>[needs update]
In April 2022, TSMC announced its GAAFET N2 process technology would enter risk production phase at the end of 2024 and production phase in 2025.<a class="footnote-ref" id="fnref:37" href="#fn:37">37</a> In July 2022, TSMC announced that its N2 process technology was expected to feature <a href="/facts/Backside_power_delivery/Fw9XIeam">backside power delivery</a> and was expected to offer 10–15% higher performance at iso power or 20–30% lower power at iso performance and over 20% higher transistor density compared to N3E.<a class="footnote-ref" id="fnref:38" href="#fn:38">38</a>[needs update]
In July 2022, Samsung made a number of disclosures regarding the company's previously forthcoming process technology called "2GAP" (2nm Gate All-around Production): the process previously remained on track for 2025 launch into mass production; number of nanosheets was projected to increase from 3 in "3GAP" to 4; the company worked on several improvements of metallization, namely "single-grain metal" for low-resistance vias and direct-etched metal interconnect planned for 2GAP and beyond.<a class="footnote-ref" id="fnref:39" href="#fn:39">39</a>[needs update]
In August 2022, a consortium of Japanese companies funded a new venture with government support called <a href="/facts/Rapidus/H65APFps">Rapidus</a> for manufacturing of 2 nm chips. Rapidus signed agreements with <a href="/facts/IMEC/FQFKLaWL">IMEC</a><a class="footnote-ref" id="fnref:40" href="#fn:40">40</a> and <a href="/facts/IBM/QszA7nwd">IBM</a><a class="footnote-ref" id="fnref:41" href="#fn:41">41</a> in December 2022.[needs update]
In April 2023, at its Technology Symposium, TSMC introduced two more processes of its 2 nm technology platform: "N2P" featuring backside power delivery and scheduled for 2026, and "N2X" for high-performance applications. It was also revealed that the <a href="/facts/ARM_Cortex-A715/za3GDjVp">ARM Cortex-A715</a> core fabbed on the N2 process using a high-performance standard library was 16.4% faster at the same power, saved 37.2% of power at the same speed, or was ~10% faster and saved ~20% of power simultaneously at the same voltage (0.8 V) compared to the core fabbed on N3E using 3-2 fin library.<a class="footnote-ref" id="fnref:42" href="#fn:42">42</a>
In September 2024, Intel announced they would no longer be moving forward with their 20A process node, instead focusing on the development of 18A. Intel projected that avoiding ramping production of 20A could save over half a billion dollars. Intel noted that they'd successfully implemented <a href="/facts/RibbonFET/YTeIYBvc">RibbonFET</a> gate-all-around (GAA) architecture and PowerVia <a href="/facts/Backside_power_delivery/Fw9XIeam">backside power delivery</a> in their 20A process, accelerating 18A development. Intel's <a href="/facts/Arrow_Lake_(microprocessor)/AFTvbCBU">Arrow Lake</a> family of processors, which were meant to use Intel 20A, will instead have dies sourced from "external partners" and packaged by Intel.<a class="footnote-ref" id="fnref:43" href="#fn:43">43</a><a class="footnote-ref" id="fnref:44" href="#fn:44">44</a>

<h2 id="2-nm-process-nodes">2 nm process nodes</h2>
<table><tbody><tr><th></th><th colspan="4"><a href="/facts/Samsung_Electronics/STxnmHwl">Samsung</a><a class="footnote-ref" id="fnref:45" href="#fn:45">45</a><a class="footnote-ref" id="fnref:46" href="#fn:46">46</a><a class="footnote-ref" id="fnref:47" href="#fn:47">47</a><a class="footnote-ref" id="fnref:48" href="#fn:48">48</a><a class="footnote-ref" id="fnref:49" href="#fn:49">49</a></th><th colspan="3"><a href="/facts/TSMC/B4BdojRk">TSMC</a></th><th colspan="2"><a href="/facts/Intel/SMF0gJJX">Intel</a></th></tr><tr><th>Process name</th><td>SF2</td><td>SF2P</td><td>SF2X</td><td>SF2Z</td><td>N2</td><td>N2P</td><td>N2X</td><td>20A</td><td>18A</td></tr><tr><th>Transistor type</th><td colspan="4"><a href="/facts/MBCFET/YTeIYBvc">MBCFET</a></td><td colspan="3"><a href="/facts/GAAFET/YTeIYBvc">GAAFET</a></td><td colspan="2"><a href="/facts/RibbonFET/YTeIYBvc">RibbonFET</a></td></tr><tr><th>Transistor density (MTr/mm2)</th><td>231<a class="footnote-ref" id="fnref:50" href="#fn:50">50</a></td><td>Unknown</td><td>Unknown</td><td>Unknown</td><td colspan="2">313<a class="footnote-ref" id="fnref:51" href="#fn:51">51</a></td><td>Unknown</td><td>Unknown</td><td>238<a class="footnote-ref" id="fnref:52" href="#fn:52">52</a></td></tr><tr><th>SRAM bit-cell size (μm2)</th><td>Unknown</td><td>Unknown</td><td>Unknown</td><td>Unknown</td><td>0.0175<a class="footnote-ref" id="fnref:53" href="#fn:53">53</a></td><td>Unknown</td><td>Unknown</td><td>Unknown</td><td>0.021<a class="footnote-ref" id="fnref:54" href="#fn:54">54</a></td></tr><tr><th>Transistor gate pitch (nm)</th><td>Unknown</td><td>Unknown</td><td>Unknown</td><td>Unknown</td><td>Unknown</td><td>Unknown</td><td>Unknown</td><td>Unknown</td><td>50<a class="footnote-ref" id="fnref:55" href="#fn:55">55</a></td></tr><tr><th>Interconnect pitch (nm)</th><td>Unknown</td><td>Unknown</td><td>Unknown</td><td>Unknown</td><td>Unknown</td><td>Unknown</td><td>Unknown</td><td>Unknown</td><td>32<a class="footnote-ref" id="fnref:56" href="#fn:56">56</a></td></tr><tr><th>Release status</th><td>2025 volume production<a class="footnote-ref" id="fnref:57" href="#fn:57">57</a></td><td>2026 volume production</td><td>2026 volume production</td><td>2027 volume production</td><td>2024 H2 risk production<a class="footnote-ref" id="fnref:58" href="#fn:58">58</a>2025 H2 volume production<a class="footnote-ref" id="fnref:59" href="#fn:59">59</a></td><td>2026 H2 volume production<a class="footnote-ref" id="fnref:60" href="#fn:60">60</a></td><td>2027 volume production<a class="footnote-ref" id="fnref:61" href="#fn:61">61</a></td><td>2024 H1 risk production<a class="footnote-ref" id="fnref:62" href="#fn:62">62</a>2024 volume production<a class="footnote-ref" id="fnref:63" href="#fn:63">63</a><a class="footnote-ref" id="fnref:64" href="#fn:64">64</a>Canceled 2024<a class="footnote-ref" id="fnref:65" href="#fn:65">65</a></td><td>2025 H1 risk production<a class="footnote-ref" id="fnref:66" href="#fn:66">66</a>2025 H2 volume production<a class="footnote-ref" id="fnref:67" href="#fn:67">67</a></td></tr></tbody></table>
<h2 id="beyond-2-nm">Beyond 2 nm</h2>
In July 2021, <a href="/facts/Intel/SMF0gJJX">Intel</a> reported that they planned 18A production for 2025.<a class="footnote-ref" id="fnref:68" href="#fn:68">68</a> Intel's February 2022 roadmap added that 18A was previously expected to have delivered 10% improvement in performance per watt compared to Intel 20A.<a class="footnote-ref" id="fnref:69" href="#fn:69">69</a> <a href="/facts/Intel/SMF0gJJX">Intel</a>'s August 2024 newsroom announcement further indicated that the 18A process should be manufacturing-ready for 2025 H1.<a class="footnote-ref" id="fnref:70" href="#fn:70">70</a>
In December 2021, vertical-transport FET (VTFET) CMOS logic transistor design with a vertical nanosheet was demonstrated at sub-45 nm gate pitch.<a class="footnote-ref" id="fnref:71" href="#fn:71">71</a>
In May 2022, <a href="/facts/IMEC/FQFKLaWL">IMEC</a> presented a process technology roadmap which extends the current biannual cadence of node introduction and square-root-of-two node naming rule to 2036. The roadmap ends with process node "A2" (meant to represent a 2 angstrom node), named by analogy with TSMC's naming scheme to be introduced by then.<a class="footnote-ref" id="fnref:72" href="#fn:72">72</a>
Apart from the expected shrinking of transistor structures and interconnects, innovations forecasted by IMEC were as follows:[needs update] 

<ul><li>Transistor architecture (forksheet FET, CFET, CFET with atomic (2D material) channel);</li>
<li>Deployment of high-<a href="/facts/Numerical_aperture/EvW1oVBC">NA</a> (0.55) <a href="/facts/Extreme_ultraviolet_lithography/NHpdP37J">EUV</a> tools with the first $400 million tool to be completed at <a href="/facts/ASML_Holding/1ARIwdbM">ASML</a> in 2023, and the first production tool was shipped to and installed at Intel in 2024;<a class="footnote-ref" id="fnref:73" href="#fn:73">73</a></li>
<li>Further reduction of standard cell height (eventually to "less than 4" tracks);</li>
<li>Back-side power distribution, buried power rails;</li>
<li>New materials (<a href="/facts/Ruthenium/uzCm4ufn">ruthenium</a> for metallization (interconnects), graphene, <a href="/facts/Tungsten_disulfide/4LKKGryS">WS2</a> <a href="/facts/Transition_metal_dichalcogenide_monolayers/hz7oyw2H">monolayer</a> for atomic channel);</li>
<li>New manufacturing techniques (subtractive metallization, direct metal etch);</li>
<li>Air gaps to further reduce relative permittivity of intermetal dielectric and, therefore, interconnect capacitance;</li>
<li>IC design innovations (2.5D chiplets, 3D interconnect), more advanced EDA tools.</li></ul>
In September 2022, <a href="/facts/Samsung_Electronics/STxnmHwl">Samsung</a> presented their future business goals, which at that time included an aim to mass-produce 1.4 nm by 2027.<a class="footnote-ref" id="fnref:74" href="#fn:74">74</a>
As of 2023, Intel, TSMC and Samsung have all demonstrated CFET transistors. These transistors are made up of two stacked horizontal nanosheet transistors, one transistor is of the p-type (a pFET transistor) and the other transistor is of the n-type (an nFET transistor).<a class="footnote-ref" id="fnref:75" href="#fn:75">75</a>

<h2 id="notes">Notes</h2>

<h2 id="further-reading">Further reading</h2>
<ul><li>Merritt, Rick (26 March 2018), <a href="https://www.eetasia.com/18032601-2nm-end-of-the-road/">"2nm: End of the Road ?"</a>, www.eetasia.com</li></ul>
<table><tbody><tr><td>Preceded by<a href="/facts/3_nm_process/zR3mn68L">"3 nm"</a> (<a href="/facts/FinFET/xox63kP7">FinFET</a>/<a href="/facts/GAAFET/YTeIYBvc">GAAFET</a>)</td><td><a href="/facts/MOSFET/eTDJT2Km">MOSFET</a> <a href="/facts/Semiconductor_device_fabrication/Jd23Mu1z">semiconductor device fabrication</a> process</td><td>Succeeded by<a href="/facts/1_nm_process/nvmYmN76">"1 nm"</a> (<a href="/facts/FinFET/xox63kP7">FinFET</a>/<a href="/facts/GAAFET/YTeIYBvc">GAAFET</a>)</td></tr></tbody></table>

<h2 id="references">References</h2>

<ol>
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<li id="fn:47">"Samsung Foundry Update: 2nm Unveil in June, Second-Gen SF3 3nm Hits Production This Year". <a href="https://www.anandtech.com/show/21377/samsung-foundry-update-2nm-unveil-in-june-2nd-gen-3nm-hits-production-this-year" target="_blank">https://www.anandtech.com/show/21377/samsung-foundry-update-2nm-unveil-in-june-2nd-gen-3nm-hits-production-this-year</a> <a href="#fnref:47" class="footnote-back-ref">↩</a></li>
<li id="fn:48">"Samsung Foundry Unveils Updated Roadmap: BSPDN and 2nm Evolution Through 2027". <a href="https://www.anandtech.com/show/21444/samsung-foundry-unveils-updated-roadmap-2nm-evolution-through-2027" target="_blank">https://www.anandtech.com/show/21444/samsung-foundry-unveils-updated-roadmap-2nm-evolution-through-2027</a> <a href="#fnref:48" class="footnote-back-ref">↩</a></li>
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<li id="fn:53">SRAM scaling isn't dead after all — TSMC's 2nm process tech claims major improvements <a href="https://www.tomshardware.com/tech-industry/sram-scaling-isnt-dead-after-all-tsmcs-2nm-process-tech-claims-major-improvements" target="_blank">https://www.tomshardware.com/tech-industry/sram-scaling-isnt-dead-after-all-tsmcs-2nm-process-tech-claims-major-improvements</a> <a href="#fnref:53" class="footnote-back-ref">↩</a></li>
<li id="fn:54">A 0.021μm² High-Density SRAM in Intel-18A-RibbonFET Technology with PowerVia-Backside Power Delivery (19 Feb 2025) <a href="https://submissions.mirasmart.com/ISSCC2025/PDF/ISSCC2025AdvanceProgram.pdf" target="_blank">https://submissions.mirasmart.com/ISSCC2025/PDF/ISSCC2025AdvanceProgram.pdf</a> <a href="#fnref:54" class="footnote-back-ref">↩</a></li>
<li id="fn:55">"25 % schneller oder 36 % sparsamer: Intel vergleicht Intel 18A gegen Intel 3". <a href="https://www.hardwareluxx.de/index.php/news/hardware/prozessoren/66415-25-schneller-oder-36-sparsamer-intel-vergleicht-intel-18a-gegen-intel-3.html" target="_blank">https://www.hardwareluxx.de/index.php/news/hardware/prozessoren/66415-25-schneller-oder-36-sparsamer-intel-vergleicht-intel-18a-gegen-intel-3.html</a> <a href="#fnref:55" class="footnote-back-ref">↩</a></li>
<li id="fn:56">"25 % schneller oder 36 % sparsamer: Intel vergleicht Intel 18A gegen Intel 3". <a href="https://www.hardwareluxx.de/index.php/news/hardware/prozessoren/66415-25-schneller-oder-36-sparsamer-intel-vergleicht-intel-18a-gegen-intel-3.html" target="_blank">https://www.hardwareluxx.de/index.php/news/hardware/prozessoren/66415-25-schneller-oder-36-sparsamer-intel-vergleicht-intel-18a-gegen-intel-3.html</a> <a href="#fnref:56" class="footnote-back-ref">↩</a></li>
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<li id="fn:59">"TSMC 2nm Update: N2 in 2025, N2P Loses Backside Power, and NanoFlex Brings Optimal Cells". <a href="https://www.anandtech.com/show/21370/tsmc-2nm-update-n2-in-2025-n2p-loses-bspdn-nanoflex-optimizations" target="_blank">https://www.anandtech.com/show/21370/tsmc-2nm-update-n2-in-2025-n2p-loses-bspdn-nanoflex-optimizations</a> <a href="#fnref:59" class="footnote-back-ref">↩</a></li>
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<li id="fn:68">Cutress, Dr Ian (26 July 2021). "Intel's Process Roadmap to 2025: with 4nm, 3nm, 20A and 18A?!". www.anandtech.com. Archived from the original on 3 November 2021. Retrieved 27 July 2021. <a href="https://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros" target="_blank">https://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros</a> <a href="#fnref:68" class="footnote-back-ref">↩</a></li>
<li id="fn:69">Alcorn, Paul (4 September 2024). "Intel announces cancellation of 20A process node for Arrow Lake, goes with external nodes instead, likely TSMC [Updated]". Tom's Hardware. Retrieved 10 September 2024. <a href="https://www.tomshardware.com/pc-components/cpus/intel-announces-cancellation-of-20a-process-node-for-arrow-lake-goes-with-external-nodes-instead-likely-tsmc" target="_blank">https://www.tomshardware.com/pc-components/cpus/intel-announces-cancellation-of-20a-process-node-for-arrow-lake-goes-with-external-nodes-instead-likely-tsmc</a> <a href="#fnref:69" class="footnote-back-ref">↩</a></li>
<li id="fn:70">"Intel 18A powered on and healthy, on track for next-gen client and server chip production next year" (Press release). Intel. 6 August 2024. <a href="https://www.intel.com/content/www/us/en/newsroom/news/intel-foundry-achieves-major-milestones.html" target="_blank">https://www.intel.com/content/www/us/en/newsroom/news/intel-foundry-achieves-major-milestones.html</a> <a href="#fnref:70" class="footnote-back-ref">↩</a></li>
<li id="fn:71">Jagannathan, H.; et al. (2021). "Vertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices". 2021 IEEE International Electron Devices Meeting (IEDM). pp. 26.1.1–26.1.4. doi:10.1109/IEDM19574.2021.9720561. ISBN 978-1-6654-2572-8. S2CID 247321213. <a href="978-1-6654-2572-8" target="_blank">978-1-6654-2572-8</a> <a href="#fnref:71" class="footnote-back-ref">↩</a></li>
<li id="fn:72">"Imec Presents Sub-1nm Process and Transistor Roadmap Until 2036". Tom's Hardware. 21 May 2022. <a href="https://www.tomshardware.com/news/imecs-sub-1nm-process-node-and-transistor-roadmap-until-2036-from-nanometers-to-the-angstrom-era" target="_blank">https://www.tomshardware.com/news/imecs-sub-1nm-process-node-and-transistor-roadmap-until-2036-from-nanometers-to-the-angstrom-era</a> <a href="#fnref:72" class="footnote-back-ref">↩</a></li>
<li id="fn:73">"High NA EUV at Intel" (Press release). Retrieved 27 September 2024. <a href="https://www.intel.com/content/www/us/en/newsroom/resources/intel-high-na-euv.html" target="_blank">https://www.intel.com/content/www/us/en/newsroom/resources/intel-high-na-euv.html</a> <a href="#fnref:73" class="footnote-back-ref">↩</a></li>
<li id="fn:74">"Samsung Electronics Unveils Plans for 1.4nm Process Technology and Investment for Production Capacity at Samsung Foundry Forum 2022" (Press release). Samsung. 4 October 2022. <a href="https://news.samsung.com/global/samsung-electronics-unveils-plans-for-1-4nm-process-technology-and-investment-for-production-capacity-at-samsung-foundry-forum-2022" target="_blank">https://news.samsung.com/global/samsung-electronics-unveils-plans-for-1-4nm-process-technology-and-investment-for-production-capacity-at-samsung-foundry-forum-2022</a> <a href="#fnref:74" class="footnote-back-ref">↩</a></li>
<li id="fn:75">"Intel, Samsung, and TSMC Demo 3D-Stacked Transistors - IEEE Spectrum". <a href="https://spectrum.ieee.org/cfet-intel-samsung-tsmc" target="_blank">https://spectrum.ieee.org/cfet-intel-samsung-tsmc</a> <a href="#fnref:75" class="footnote-back-ref">↩</a></li>
</ol>

2 nm process open-in-new

2 nm process