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Teardrop (electronics)
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<h2 id="purpose">Purpose</h2> <p>The main purpose of teardrops is to enhance <a href="/facts/Structural_integrity/5aYoMIlw">structural integrity</a> in presence of thermal or <a href="/facts/Mechanical_stress/ErAXDbbd">mechanical stresses</a>,<a class="footnote-ref" id="fnref:1" href="#fn:1"><sup>1</sup></a><a class="footnote-ref" id="fnref:2" href="#fn:2"><sup>2</sup></a><a class="footnote-ref" id="fnref:3" href="#fn:3"><sup>3</sup></a> for example due to vibration or flexing.<a class="footnote-ref" id="fnref:4" href="#fn:4"><sup>4</sup></a> Structural integrity may be compromised, e.g., by misalignment during drilling, so that too much <a href="/facts/Copper/I8PEE8oX">copper</a> may be removed by the drill hole in the area where a trace connects to the pad or via.<a class="footnote-ref" id="fnref:5" href="#fn:5"><sup>5</sup></a><a class="footnote-ref" id="fnref:6" href="#fn:6"><sup>6</sup></a><a class="footnote-ref" id="fnref:7" href="#fn:7"><sup>7</sup></a> An extra advantage is the enlarging of manufacturing tolerances, making manufacturing easier and cheaper.<a class="footnote-ref" id="fnref:8" href="#fn:8"><sup>8</sup></a> </p> <h2 id="shape">Shape</h2> <p> While a typical shape of a teardrop is straight-line tapering, they may be concave.<a class="footnote-ref" id="fnref:9" href="#fn:9"><sup>9</sup></a> This type of teardrop is also called <i>filleting</i> or <i>straight</i>.<a class="footnote-ref" id="fnref:10" href="#fn:10"><sup>10</sup></a> To produce a <i><a href="/facts/Snowman/4Bm4tP34">snowman</a></i>-shaped teardrop, a secondary pad of smaller size is added at the junction overlapping with the primary pad (hence the nickname).<a class="footnote-ref" id="fnref:11" href="#fn:11"><sup>11</sup></a><a class="footnote-ref" id="fnref:12" href="#fn:12"><sup>12</sup></a> </p> <h2 id="necking">Necking</h2> <p class="note">See also: <a href="/facts/Necking_(engineering)/wwG8GIav">Necking (engineering)</a></p> <p>For similar reasons, a technique called <i>trace necking</i> reduces (or <i>necks down</i><a class="footnote-ref" id="fnref:13" href="#fn:13"><sup>13</sup></a><a class="footnote-ref" id="fnref:14" href="#fn:14"><sup>14</sup></a><a class="footnote-ref" id="fnref:15" href="#fn:15"><sup>15</sup></a>) the width of a trace that approaches a narrower pad of a <a href="/facts/Surface-mounted_device/SjFyQbbm">surface-mounted device</a> or a <a href="/facts/Through-hole/q0d03wve">through-hole</a> with a diameter that is less than the width of the trace, or when the trace passes through bottlenecks (for example, between the pads of a component).<a class="footnote-ref" id="fnref:16" href="#fn:16"><sup>16</sup></a><a class="footnote-ref" id="fnref:17" href="#fn:17"><sup>17</sup></a><a class="footnote-ref" id="fnref:18" href="#fn:18"><sup>18</sup></a><a class="footnote-ref" id="fnref:19" href="#fn:19"><sup>19</sup></a> </p> <h2 id="external-links">External links</h2> Wikimedia Commons has media related to Teardrop (electronics). <ul><li><a href="https://www.fastlink-electronics.com/products/high-frequency-pcb-hfp/">High Frequency PCB</a></li></ul> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>Wahby, Mahmoud (2014-02-21). "Component placement tips and strategies". EDN Network. Archived from the original on 2017-09-24. Retrieved 2017-09-24. <a href="http://www.edn.com/design/pc-board/4428665/2/Component-placement-tips-and-strategies" target="_blank">http://www.edn.com/design/pc-board/4428665/2/Component-placement-tips-and-strategies</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>Loughhead, Phil (2017-05-30). "Removing Unused Pads and Adding Teardrops". Altium Designer technical documentation. Altium. Archived from the original on 2017-09-24. Retrieved 2017-09-24. <a href="http://www.altium.com/documentation/17.1/display/ADES/((Removing+Unused+Pads+and+Adding+Teardrops))_AD" target="_blank">http://www.altium.com/documentation/17.1/display/ADES/((Removing+Unused+Pads+and+Adding+Teardrops))_AD</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li> <li id="fn:3"><p>Kolath, Amos (2010). "Why Where When and how teardrops should be added to PCB?". KaiZen Technologies. Archived from the original on 2017-09-24. Retrieved 2017-09-24. <a href="http://www.kaizen-t.com/technical/teardropinpcb.html" target="_blank">http://www.kaizen-t.com/technical/teardropinpcb.html</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li> <li id="fn:4"><p>Ruth (2023-04-28). "Introduction to high speed PCB and is it same as high frequency PCB". IBE Electronics. Retrieved 2023-05-01. <a href="https://www.pcbaaa.com/an-ultimate-introduction-to-high-speed-pcb-and-is-it-same-as-high-frequency-pcb/" target="_blank">https://www.pcbaaa.com/an-ultimate-introduction-to-high-speed-pcb-and-is-it-same-as-high-frequency-pcb/</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li> <li id="fn:5"><p>Loughhead, Phil (2017-05-30). "Removing Unused Pads and Adding Teardrops". Altium Designer technical documentation. Altium. Archived from the original on 2017-09-24. Retrieved 2017-09-24. <a href="http://www.altium.com/documentation/17.1/display/ADES/((Removing+Unused+Pads+and+Adding+Teardrops))_AD" target="_blank">http://www.altium.com/documentation/17.1/display/ADES/((Removing+Unused+Pads+and+Adding+Teardrops))_AD</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></p></li> <li id="fn:6"><p>Kolath, Amos (2010). "Why Where When and how teardrops should be added to PCB?". KaiZen Technologies. Archived from the original on 2017-09-24. Retrieved 2017-09-24. <a href="http://www.kaizen-t.com/technical/teardropinpcb.html" target="_blank">http://www.kaizen-t.com/technical/teardropinpcb.html</a> <a href="#fnref:6" class="footnote-back-ref">↩</a></p></li> <li id="fn:7"><p>Lobner, Wilhelm (October 2002). "Empfehlung zu Tear-drops" [Recommendations for tear-drops] (PDF) (in German). AT&S AG. Archived (PDF) from the original on 2017-09-24. Retrieved 2017-09-24. <a href="http://wiki.fed.de/images/5/50/Empfehlung_zu_Tear-drops.pdf" target="_blank">http://wiki.fed.de/images/5/50/Empfehlung_zu_Tear-drops.pdf</a> <a href="#fnref:7" class="footnote-back-ref">↩</a></p></li> <li id="fn:8"><p>Kolath, Amos (2010). "Why Where When and how teardrops should be added to PCB?". KaiZen Technologies. Archived from the original on 2017-09-24. Retrieved 2017-09-24. <a href="http://www.kaizen-t.com/technical/teardropinpcb.html" target="_blank">http://www.kaizen-t.com/technical/teardropinpcb.html</a> <a href="#fnref:8" class="footnote-back-ref">↩</a></p></li> <li id="fn:9"><p>Loughhead, Phil (2017-05-30). "Removing Unused Pads and Adding Teardrops". Altium Designer technical documentation. Altium. Archived from the original on 2017-09-24. Retrieved 2017-09-24. <a href="http://www.altium.com/documentation/17.1/display/ADES/((Removing+Unused+Pads+and+Adding+Teardrops))_AD" target="_blank">http://www.altium.com/documentation/17.1/display/ADES/((Removing+Unused+Pads+and+Adding+Teardrops))_AD</a> <a href="#fnref:9" class="footnote-back-ref">↩</a></p></li> <li id="fn:10"><p>Kolath, Amos (2010). "Why Where When and how teardrops should be added to PCB?". KaiZen Technologies. Archived from the original on 2017-09-24. Retrieved 2017-09-24. <a href="http://www.kaizen-t.com/technical/teardropinpcb.html" target="_blank">http://www.kaizen-t.com/technical/teardropinpcb.html</a> <a href="#fnref:10" class="footnote-back-ref">↩</a></p></li> <li id="fn:11"><p>Kolath, Amos (2010). "Why Where When and how teardrops should be added to PCB?". KaiZen Technologies. Archived from the original on 2017-09-24. Retrieved 2017-09-24. <a href="http://www.kaizen-t.com/technical/teardropinpcb.html" target="_blank">http://www.kaizen-t.com/technical/teardropinpcb.html</a> <a href="#fnref:11" class="footnote-back-ref">↩</a></p></li> <li id="fn:12"><p>Gutierrez, Keith G.; Coates, Keven (June 2010). "PCB Design Guidelines for 0.5mm Package-on-Package Applications Processor, Part I" (PDF). Texas Instruments. Application Report SPRABB3. Archived (PDF) from the original on 2017-09-24. Retrieved 2015-07-27. <a href="http://www.ti.com/lit/an/sprabb3/sprabb3.pdf" target="_blank">http://www.ti.com/lit/an/sprabb3/sprabb3.pdf</a> <a href="#fnref:12" class="footnote-back-ref">↩</a></p></li> <li id="fn:13"><p>Loughhead, Phil (2017-04-25). "Interactive Routing". Altium Designer technical documentation. Altium. Archived from the original on 2017-09-24. Retrieved 2017-09-24. <a href="http://www.altium.com/documentation/17.1/display/ADES/((Interactive+Routing))_AD" target="_blank">http://www.altium.com/documentation/17.1/display/ADES/((Interactive+Routing))_AD</a> <a href="#fnref:13" class="footnote-back-ref">↩</a></p></li> <li id="fn:14"><p>Byers, T. J. (1991-08-01). Printed Circuit Board Design with Microcomputers (1 ed.). McGraw-Hill Book Company. p. 102. ISBN 0070095582. LCCN 91-72187. <a href="0070095582" target="_blank">0070095582</a> <a href="#fnref:14" class="footnote-back-ref">↩</a></p></li> <li id="fn:15"><p>Kollipara, Ravindranath; Tripathi, Vijai K.; Sergent, Jerry E.; Blackwell, Glenn R.; White, Donald; Staszak, Zbigniew J. (2005). "11.1.3 Packaging Electronic Systems - Design of Printed Wiring Boards" (PDF). In Whitaker, Jerry C.; Dorf, Richard C. (eds.). The Electronics Handbook (2 ed.). CRC Press. p. 1266. ISBN 978-0-8493-1889-4. LCCN 2004057106. Archived (PDF) from the original on 2017-09-25. Retrieved 2017-09-25. <a href="978-0-8493-1889-4" target="_blank">978-0-8493-1889-4</a> <a href="#fnref:15" class="footnote-back-ref">↩</a></p></li> <li id="fn:16"><p>Byers, T. J. (1991-08-01). Printed Circuit Board Design with Microcomputers (1 ed.). McGraw-Hill Book Company. p. 102. ISBN 0070095582. LCCN 91-72187. <a href="0070095582" target="_blank">0070095582</a> <a href="#fnref:16" class="footnote-back-ref">↩</a></p></li> <li id="fn:17"><p>Kollipara, Ravindranath; Tripathi, Vijai K.; Sergent, Jerry E.; Blackwell, Glenn R.; White, Donald; Staszak, Zbigniew J. (2005). "11.1.3 Packaging Electronic Systems - Design of Printed Wiring Boards" (PDF). In Whitaker, Jerry C.; Dorf, Richard C. (eds.). The Electronics Handbook (2 ed.). CRC Press. p. 1266. ISBN 978-0-8493-1889-4. LCCN 2004057106. Archived (PDF) from the original on 2017-09-25. Retrieved 2017-09-25. <a href="978-0-8493-1889-4" target="_blank">978-0-8493-1889-4</a> <a href="#fnref:17" class="footnote-back-ref">↩</a></p></li> <li id="fn:18"><p>US 3560256, Abrams, Halle, "Packaging Electronic Systems", published 1971-02-02, assigned to Western Electric Co. <a href="https://worldwide.espacenet.com/textdoc?DB=EPODOC&IDX=US3560256" target="_blank">https://worldwide.espacenet.com/textdoc?DB=EPODOC&IDX=US3560256</a> <a href="#fnref:18" class="footnote-back-ref">↩</a></p></li> <li id="fn:19"><p>Thierauf, Stephen C. (2004). High-Speed Circuit Board Signal Integrity (1 ed.). Artech House, Inc. pp. 104–105. ISBN 1580531318. <a href="1580531318" target="_blank">1580531318</a> <a href="#fnref:19" class="footnote-back-ref">↩</a></p></li> </ol>