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Serial computer
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<h2 id="serial-machines">Serial machines</h2> <ul><li><a href="/facts/EDVAC/6DHxuu2d">EDVAC</a> (1949)</li> <li><a href="/facts/BINAC/oKT7mjAR">BINAC</a> (1949)</li> <li><a href="/facts/SEAC_(computer)/Hkt7UCJx">SEAC</a> (1950)</li> <li><a href="/facts/UNIVAC_I/LQzozqY2">UNIVAC I</a> (1951)</li> <li><a href="/facts/Elliott_Brothers_(computer_company)/rN9mTIhk">Elliott Brothers</a> <a href="/facts/Elliott_152/q00qJYLL">Elliott 152</a> (1954)</li> <li><a href="/facts/Bendix_G-15/QMFMfpLW">Bendix G-15</a> (1956)</li> <li><a href="/facts/LGP-30/R0p7wtmV">LGP-30</a> (1956)<a class="footnote-ref" id="fnref:3" href="#fn:3"><sup>3</sup></a></li> <li><a href="/facts/Elliott_Brothers_(computer_company)/rN9mTIhk">Elliott Brothers</a> <a href="/facts/Elliott_803/m8TIrlxn">Elliott 803</a> (1958)</li> <li><a href="/facts/ZEBRA_(computer)/gho7QQFE">ZEBRA</a> (1958)</li> <li><a href="/facts/D-17B/vFCL4t6W">D-17B</a> guidance computer (1962)</li> <li><a href="/facts/PDP-8%2fS/udvrynE8">PDP-8/S</a><a class="footnote-ref" id="fnref:4" href="#fn:4"><sup>4</sup></a> (1966)</li> <li>General Electric GE-PAC 4040 process control computer</li> <li><a href="/facts/F14_CADC/DD0EPEF9">F14 CADC</a> (1970) – transferred all data serially, but internally operated on many bits in parallel<a class="footnote-ref" id="fnref:5" href="#fn:5"><sup>5</sup></a></li> <li><a href="/facts/Kenbak-1/uSxe6Lpr">Kenbak-1</a> (1971)</li> <li><a href="/facts/Datapoint_2200/laFBj52J">Datapoint 2200</a> (1971)<a class="footnote-ref" id="fnref:6" href="#fn:6"><sup>6</sup></a></li> <li><a href="/facts/HP-35/EKPVBVe1">HP-35</a> (1972)<a class="footnote-ref" id="fnref:7" href="#fn:7"><sup>7</sup></a></li> <li>Digit-serial <a href="/facts/HP_Saturn/jHVxcXpF">HP Saturn</a>-based calculators<a class="footnote-ref" id="fnref:8" href="#fn:8"><sup>8</sup></a> from the <a href="/facts/HP-71B/ccrWaMev">HP-71B</a> (1974) to the <a href="/facts/HP_50g/CHJ2toxY">HP 50g</a> (2006–2015)</li> <li><a href="/facts/National_Semiconductor_SC%2fMP/V69qf9Wz">National Semiconductor SC/MP</a> (1976)</li> <li><a href="/facts/Ferranti_F100-L/AAN06Hgx">Ferranti F100-L</a> (1977) – <a href="/facts/16-bit_computing/bTGS44Ne">16-bit</a>, but uses a bit-serial <a href="/facts/Arithmetic_logic_unit/SgIjPzSc">arithmetic logic unit</a></li></ul> <h3>Massively parallel</h3> <p>Most of the early <a href="/facts/Massively_parallel_(computing)/dX7W2Nxs">massive parallel processing</a> machines were built out of individual serial processors, including: </p> <ul><li><a href="/facts/ICL_Distributed_Array_Processor/FDIAD68S">ICL Distributed Array Processor</a> (1979)</li> <li><a href="/facts/Goodyear_MPP/5kC1NPRh">Goodyear MPP</a> (1983)</li> <li><a href="/facts/Connection_Machine/wxUPNe4r">Connection Machine</a> CM-1 (1985)</li> <li>Connection Machine CM-2 (1987)</li> <li><a href="/facts/MasPar/mPosuqps">MasPar</a> MP-1 (1990) – 32-bit architecture, internally processed 4 bits at a time<a class="footnote-ref" id="fnref:9" href="#fn:9"><sup>9</sup></a></li> <li>VIRAM1 <a href="/facts/Computational_RAM/gHREbDr0">computational RAM</a> (2003)</li></ul> <h2 id="see-also">See also</h2> <ul><li><a href="/facts/1-bit_computing/ArKvhVbw">1-bit computing</a></li> <li><a href="/facts/BKM_algorithm/e0r1Wszn">BKM algorithm</a></li> <li><a href="/facts/CORDIC_algorithm/sQqTjkd2">CORDIC algorithm</a></li></ul> <h2 id="further-reading">Further reading</h2> <ul><li><a href="/facts/Richard_I._Hartley/w4qz5PCR">Hartley, Richard I.</a>; Parhi, Keshab K. (1995). <i>Digit-Serial Computation</i>. The Kluwer International Series in Engineering and Computer Science (1 ed.). Norwell, Massachusetts, USA: <a href="/facts/Kluwer_Academic_Publishers/nAesf6nT">Kluwer Academic Publishers</a>. <a href="/facts/ISBN_(identifier)/15AdSPa9">ISBN</a> 0-7923-9573-5. SECS316. (xiv+306 pages)</li> <li>Parhi, Keshab K. (April 1991). "A Systematic Approach for Design of Digit-Serial Signal Processing Architectures". <i><a href="/facts/IEEE_Transactions_on_Circuits_and_Systems/Un7v2Tdv">IEEE Transactions on Circuits and Systems</a></i>. 38 (4): 358–375. <a href="/facts/Doi_(identifier)/muM9Etpq">doi</a>:<a href="https://doi.org/10.1109%2F31.75394">10.1109/31.75394</a>. (8 pages)</li></ul> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>Wilkes, Maurice Vincent (1956). Automatic digital computers. Methuen Publishing Ltd / John Wiley & Sons, Inc. Retrieved 2012-06-06. <a href="/wiki/Maurice_Vincent_Wilkes" target="_blank">/wiki/Maurice_Vincent_Wilkes</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>Howe, Richard James (2020) [2019-06-27]. "Bit-Serial: A bit-serial CPU written in VHDL, with a simulator written in C." Github Project: A Bit Serial CPU. Archived from the original on 2022-06-15. Retrieved 2019-06-28. <a href="https://github.com/howerj/bit-serial" target="_blank">https://github.com/howerj/bit-serial</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li> <li id="fn:3"><p>Miller, Raymond E. (1965). Switching Theory – Volume 1: Combinational Circuits. Vol. 1 (Second printing, March 1966, of 1st ed.). John Wiley & Sons, Inc. pp. 44–47. LCCN 65-14249. <a href="/wiki/John_Wiley_%26_Sons,_Inc." target="_blank">/wiki/John_Wiley_%26_Sons,_Inc.</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li> <li id="fn:4"><p>Nineteen Fifty-Seven to the Present (PDF) (6 ed.). Maynard, Massachusetts, USA: Digital Equipment Corporation. 1978 [1972]. p. 7. Archived (PDF) from the original on 2022-03-02. Retrieved 2021-02-06. (1+viii+87+3 pages) <a href="http://www.bitsavers.org/pdf/dec/_Books/DEC_1957_To_The_Present_1978.pdf" target="_blank">http://www.bitsavers.org/pdf/dec/_Books/DEC_1957_To_The_Present_1978.pdf</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li> <li id="fn:5"><p>Holt, Raymond M. (1971). This paper describes the architecture of the CPU and Memory for the Central Air Data Computer (CADC) System used in the Grumman/Navy F14A carrier-based fighter aircraft (PDF). pp. 5, 7. AP1-26-97. Archived from the original (PDF) on 2017-11-04. Retrieved 2017-11-04. […] the processor was designed to transfer data serially throughout the entire system. […] The Parallel Multiplier Unit […] by means of a parallel algorithm […] (26 pages) <a href="/wiki/Raymond_M._Holt" target="_blank">/wiki/Raymond_M._Holt</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></p></li> <li id="fn:6"><p>Shirriff, Ken (May 2015). "The Texas Instruments TMX 1795: the (almost) first, forgotten microprocessor". Archived from the original on 2022-06-15. Retrieved 2020-05-29. Even operating one bit at a time as a serial computer, the Datapoint 2200 performed considerably faster than the 8008 chip... <a href="https://www.righto.com/2015/05/the-texas-instruments-tmx-1795-first.html" target="_blank">https://www.righto.com/2015/05/the-texas-instruments-tmx-1795-first.html</a> <a href="#fnref:6" class="footnote-back-ref">↩</a></p></li> <li id="fn:7"><p>Whitney, Thomas M. (1975). "Part I. Basic Computer Architecture. / Chapter 3. Introduction to Calculators: / 3-5. Example Systems / The Hewlett Packard HP-35". In Stone, Harold Stuart (ed.). Introduction to Computer Architecture. Computer Sciences Series (1 ed.). Science Research Associates, Inc. (SRA). pp. 118–135 [123–135]. ISBN 0-574-18405-8. LCCN 75-14016. ark:/13960/t8pc40t3q. Order-Code 13-4005. Retrieved 2023-09-29. p. 124: […] The HP-35 is a totally serial computer. The adder is a BCD serial type […] The serial structure means less integrated circuit area must be allocated to interconnection lines and gating functions and an interesting trade off occurs. A bit-serial, digit-serial architecture is inherently one fourth the speed of a bit-parallel digit-serial structure […] But the basic clock rate for a bit-serial structure can sometimes be increased since additional area can be allocated for larger integrated devices that are necessary for greater speed. In the HP-35, the execution time of the most complex functions is under one second, while the serial architecture permits an increased circuit complexity. […] Instructions in the HP-35 are transferred serially from the active read-only memory to the arithmetic and control circuits and to other ROMs if present. […] <a href="0-574-18405-8" target="_blank">0-574-18405-8</a> <a href="#fnref:7" class="footnote-back-ref">↩</a></p></li> <li id="fn:8"><p>Smith, Eric L. "Brouhaha" (2023-08-09). "HP-15C CE woes: 1 bug, 2 limitations, 3 questions". MoHPC - The Museum of HP Calculators. Archived from the original on 2023-08-10. Retrieved 2023-09-24. <a href="https://www.hpmuseum.org/forum/thread-20281.html" target="_blank">https://www.hpmuseum.org/forum/thread-20281.html</a> <a href="#fnref:8" class="footnote-back-ref">↩</a></p></li> <li id="fn:9"><p>Culver, John (2014-09-05). "MasPar: Massively Parallel Computers – 32 cores on a chip". Archived from the original on 2022-06-15. Retrieved 2022-06-15. <a href="http://www.cpushack.com/2014/09/05/maspar-massively-parallel-computers-32-cores-on-a-chip/" target="_blank">http://www.cpushack.com/2014/09/05/maspar-massively-parallel-computers-32-cores-on-a-chip/</a> <a href="#fnref:9" class="footnote-back-ref">↩</a></p></li> </ol>