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32 nm process
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<h2 id="technology-demos">Technology demos</h2> <p>Prototypes using "32 nm" technology first emerged in the mid-2000s. In 2004, <a href="/facts/IBM/QszA7nwd">IBM</a> demonstrated a 0.143 μm2 <a href="/facts/Static_random-access_memory/Pmyo4V5e">SRAM</a> cell with a poly gate pitch of 135 nm, produced using <a href="/facts/Electron-beam_lithography/KILHHdKk">electron-beam lithography</a> and <a href="/facts/Photolithography/FTHsauvy">photolithography</a> on the same layer. It was observed that the cell's sensitivity to input voltage fluctuations degraded significantly at such a small scale.<a class="footnote-ref" id="fnref:10" href="#fn:10"><sup>10</sup></a> In October 2006, the <a href="/facts/Interuniversity_Microelectronics_Centre/FQFKLaWL">Interuniversity Microelectronics Centre</a> (IMEC) demonstrated a 32 nm flash patterning capability based on <a href="/facts/Double_patterning/Xk70Dxxp">double patterning</a> and <a href="/facts/Immersion_lithography/95RrUnza">immersion lithography</a>.<a class="footnote-ref" id="fnref:11" href="#fn:11"><sup>11</sup></a> The necessity of introducing double patterning and <a href="/facts/Numerical_aperture/EvW1oVBC">hyper-NA</a> tools to reduce memory cell area offset some of the cost advantages of moving to this node from the 45 nm node.<a class="footnote-ref" id="fnref:12" href="#fn:12"><sup>12</sup></a> <a href="/facts/TSMC/B4BdojRk">TSMC</a> similarly used double patterning combined with immersion lithography to produce a "32 nm" node 0.183 μm2 six-transistor SRAM cell in 2005.<a class="footnote-ref" id="fnref:13" href="#fn:13"><sup>13</sup></a> </p><p>Intel Corporation revealed its first "32 nm" test chips to the public on 18 September 2007 at the Intel Developer Forum. The test chips had a cell size of 0.182 μm2, used a second-generation <a href="/facts/High-%CE%BA_dielectric/4E8qtXmp">high-κ</a> gate dielectric and metal gate, and contained almost two billion transistors. 193 nm immersion lithography was used for the critical layers, while 193 nm or 248 nm dry lithography was used on less critical layers. The critical pitch was 112.5 nm.<a class="footnote-ref" id="fnref:14" href="#fn:14"><sup>14</sup></a> </p><p>In January 2011, Samsung completed development of the industry's first <a href="/facts/DDR4/70r37baX">DDR4</a> <a href="/facts/SDRAM/regKJe8M">SDRAM</a> module using a process technology with a size between 30 nm and 39 nm. The module could reportedly achieve data transfer rates of 2.133 Gbit/s at 1.2V, compared to 1.35V and 1.5V DDR3 DRAM at an equivalent "30 nm-class" process technology with speeds of up to 1.6 Gbit/s. The module used pseudo open drain (POD) technology, specially adapted to allow DDR4 SDRAM to consume just half the current of <a href="/facts/DDR3/1R1CTNv3">DDR3</a> when reading and writing data.<a class="footnote-ref" id="fnref:15" href="#fn:15"><sup>15</sup></a> </p> <h2 id="processors-using-32-nm-technology">Processors using "32 nm" technology</h2> <p>Intel's Core i3 and i5 processors, released in January 2010, were among the first mass-produced processors to use "32 nm" technology.<a class="footnote-ref" id="fnref:16" href="#fn:16"><sup>16</sup></a> Intel's second-generation Core processors, codenamed <a href="/facts/Sandy_Bridge/os1WwI9l">Sandy Bridge</a>, also used the "32 nm" manufacturing process. Intel's 6-core processor, codenamed <a href="/facts/Gulftown_(microprocessor)/qq85u06f">Gulftown</a> and built on the <a href="/facts/Westmere_(microarchitecture)/yB4HcYdY">Westmere</a> architecture, was released on 16 March 2010 as the Core i7 980x Extreme Edition, retailing for approximately US$1,000.<a class="footnote-ref" id="fnref:17" href="#fn:17"><sup>17</sup></a> Intel's lower-end 6-core, the i7-970, was released in late July 2010, priced at approximately US$900. Intel's "32nm" process has a transistor density of 7.11 million transistors per square milimeter (MTr/mm2).<a class="footnote-ref" id="fnref:18" href="#fn:18"><sup>18</sup></a> </p><p>AMD also released "32 nm" SOI processors in the early 2010s. AMD's FX Series processors, codenamed Zambezi and based on AMD's <a href="/facts/Bulldozer_(microarchitecture)/fUPzoGrd">Bulldozer</a> architecture, were released in October 2011. The technology utilised a "32 nm" SOI process, two CPU cores per module, and up to four modules, ranging from a quad-core design costing approximately US$130 to a $280 eight-core design. </p><p>In September 2011, <a href="/facts/Ambarella_Inc./2I4b0BBo">Ambarella Inc.</a> announced the availability of the "32 nm"-based A7L <a href="/facts/System-on-a-chip/1RVvVe6N">system-on-a-chip</a> circuit for digital still cameras, providing <a href="/facts/1080p60/Hs7cm6Mv">1080p60</a> high-definition video capabilities.<a class="footnote-ref" id="fnref:19" href="#fn:19"><sup>19</sup></a> </p> <h2 id="successor-node">Successor node</h2> <h3>28 nm & 22 nm</h3> <p>The successor to "32 nm" technology was the "22 nm" node, per the <a href="/facts/International_Technology_Roadmap_for_Semiconductors/vD2UyM3h">International Technology Roadmap for Semiconductors</a>. Intel began mass production of "22 nm" semiconductors in late 2011,<a class="footnote-ref" id="fnref:20" href="#fn:20"><sup>20</sup></a> and announced the release of its first commercial "22 nm" devices in April 2012.<a class="footnote-ref" id="fnref:21" href="#fn:21"><sup>21</sup></a><a class="footnote-ref" id="fnref:22" href="#fn:22"><sup>22</sup></a> <a href="/facts/TSMC/B4BdojRk">TSMC</a> bypassed "32 nm", jumping from "40 nm" in 2008 to "28 nm" in 2011.<a class="footnote-ref" id="fnref:23" href="#fn:23"><sup>23</sup></a> </p> <h2 id="further-reading">Further reading</h2> <ul><li>Steen, S.; et al. (2006). "Hybrid lithography: The marriage between optical and e-beam lithography. A method to study process integration and device performance for advanced device nodes". <i>Microelectronic Engineering</i>. 83 (4–9): 754–761. <a href="/facts/Doi_(identifier)/muM9Etpq">doi</a>:<a href="https://doi.org/10.1016%2Fj.mee.2006.01.181">10.1016/j.mee.2006.01.181</a>.</li></ul> <h2 id="external-links">External links</h2> <ul><li><a href="http://news.cnet.com/Chipmakers+gear+up+for+manufacturing+hurdles/2100-1006_3-6082393.html">Chipmakers gear up for manufacturing hurdles</a></li> <li><a href="http://www.sony.net/SonyInfo/News/Press/200601/06-0112E/">Sony, IBM, and Toshiba partnering on semiconductor research</a></li> <li><a href="http://www.pcworld.com/news/article/0,aid,117889,00.asp">IBM and AMD partnering on semiconductor research</a> <a href="https://web.archive.org/web/20060716191735/http://www.pcworld.com/news/article/0,aid,117889,00.asp">Archived</a> 2006-07-16 at the <a href="/facts/Wayback_Machine/nmQ3a6JC">Wayback Machine</a></li> <li><a href="http://hardware.slashdot.org/comments.pl?sid=189944&cid=15632847">Slashdot discussion</a></li> <li><a href="http://www.physorg.com/news109344893.html">Intel 32 nm process</a></li> <li><a href="http://sst.pennnet.com/display_article/309943/5/ARTCL/none/none/1/Samsung-touts-30 nm-NAND-flash-using-double-patterning/">Samsung self-aligned double patterning technology</a>[<i>permanent dead link</i>]</li></ul> <table><tbody><tr><td>Preceded by<a href="/facts/45_nm_process/hlbmxAme">45 nm</a></td><td><a href="/facts/MOSFET/eTDJT2Km">MOSFET</a> <a href="/facts/Semiconductor_device_fabrication/Jd23Mu1z">manufacturing processes</a> (<a href="/facts/CMOS/NJIWYgBl">CMOS</a>)</td><td>Succeeded by<a href="/facts/22_nm_process/zr0VI9w6">22 nm</a></td></tr></tbody></table> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>"Toshiba Makes Major Advances in NAND Flash Memory with 3-bit-per-cell 32nm generation and with 4-bit-per-cell 43nm technology". Toshiba. 11 February 2009. Retrieved 21 June 2019. <a href="http://www.toshiba.co.jp/about/press/2009_02/pr1102.htm" target="_blank">http://www.toshiba.co.jp/about/press/2009_02/pr1102.htm</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>Intel (Architecture & Silicon). Gate Dielectric Scaling for CMOS: from SiO2/PolySi to High-K/Metal-Gate. White Paper. Intel.com. Retrieved 18 June 2013. <a href="http://www.intel.com/content/www/us/en/silicon-innovations/gate-dielectric-scaling-for-cmos-guide.html" target="_blank">http://www.intel.com/content/www/us/en/silicon-innovations/gate-dielectric-scaling-for-cmos-guide.html</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li> <li id="fn:3"><p>"No More Nanometers – EEJournal". 23 July 2020. <a href="https://www.eejournal.com/article/no-more-nanometers/" target="_blank">https://www.eejournal.com/article/no-more-nanometers/</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li> <li id="fn:4"><p>Shukla, Priyank. "A Brief History of Process Node Evolution". design-reuse.com. Retrieved 9 July 2019. <a href="https://www.design-reuse.com/articles/43316/a-brief-history-of-process-node-evolution.html" target="_blank">https://www.design-reuse.com/articles/43316/a-brief-history-of-process-node-evolution.html</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li> <li id="fn:5"><p>Hruska, Joel. "14nm, 7nm, 5nm: How low can CMOS go? It depends if you ask the engineers or the economists..." ExtremeTech. <a href="https://www.extremetech.com/computing/184946-14nm-7nm-5nm-how-low-can-cmos-go-it-depends-if-you-ask-the-engineers-or-the-economists" target="_blank">https://www.extremetech.com/computing/184946-14nm-7nm-5nm-how-low-can-cmos-go-it-depends-if-you-ask-the-engineers-or-the-economists</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></p></li> <li id="fn:6"><p>"Exclusive: Is Intel Really Starting To Lose Its Process Lead? 7nm Node Slated For Release in 2022". wccftech.com. 10 September 2016. <a href="https://wccftech.com/intel-losing-process-lead-analysis-7nm-2022/" target="_blank">https://wccftech.com/intel-losing-process-lead-analysis-7nm-2022/</a> <a href="#fnref:6" class="footnote-back-ref">↩</a></p></li> <li id="fn:7"><p>"Life at 10nm. (Or is it 7nm?) And 3nm - Views on Advanced Silicon Platforms". eejournal.com. 12 March 2018. <a href="https://www.eejournal.com/article/life-at-10nm-or-is-it-7nm-and-3nm/" target="_blank">https://www.eejournal.com/article/life-at-10nm-or-is-it-7nm-and-3nm/</a> <a href="#fnref:7" class="footnote-back-ref">↩</a></p></li> <li id="fn:8"><p>"Report: Intel Scheduling 22 nm Ivy Bridge for April 2012". Tom'sHardware.com. 26 November 2011. Retrieved 5 December 2011. <a href="http://www.tomshardware.com/news/intel-ivy-bridge-22nm-cpu-3d-transistor,14093.html" target="_blank">http://www.tomshardware.com/news/intel-ivy-bridge-22nm-cpu-3d-transistor,14093.html</a> <a href="#fnref:8" class="footnote-back-ref">↩</a></p></li> <li id="fn:9"><p>"Intel's Ivy Bridge chips launch using '3D transistors'". BBC. 23 April 2012. Retrieved 18 June 2013. <a href="https://www.bbc.co.uk/news/technology-17785464" target="_blank">https://www.bbc.co.uk/news/technology-17785464</a> <a href="#fnref:9" class="footnote-back-ref">↩</a></p></li> <li id="fn:10"><p>D. M. Fried et al., IEDM 2004. <a href="#fnref:10" class="footnote-back-ref">↩</a></p></li> <li id="fn:11"><p>"IMEC demonstrates feasibility of double patterning immersion litho for 32nm node". PhysOrg.com. 18 October 2006. Retrieved 17 December 2011. <a href="http://www.physorg.com/news80410095.html" target="_blank">http://www.physorg.com/news80410095.html</a> <a href="#fnref:11" class="footnote-back-ref">↩</a></p></li> <li id="fn:12"><p>Mark LaPedus (23 February 2007). "IBM sees immersion at 22nm, pushes out EUV". EE Times. Retrieved 11 November 2011. <a href="http://www.eetimes.com/electronics-news/4069824/IBM-sees-immersion-at-22nm-pushes-out-EUV/" target="_blank">http://www.eetimes.com/electronics-news/4069824/IBM-sees-immersion-at-22nm-pushes-out-EUV/</a> <a href="#fnref:12" class="footnote-back-ref">↩</a></p></li> <li id="fn:13"><p>H-Y. Chen et al., Symp. on VLSI Tech. 2005. <a href="#fnref:13" class="footnote-back-ref">↩</a></p></li> <li id="fn:14"><p>F. T. Chen (2002). Proc. SPIE. Vol. 4889, no. 1313. <a href="#fnref:14" class="footnote-back-ref">↩</a></p></li> <li id="fn:15"><p>Peter Clarke (4 January 2011). "Samsung trials DDR4 DRAM module". EE Times. Retrieved 11 November 2011. <a href="http://www.eetimes.com/electronics-news/4211854/Samsung-trials-DDR4-DRAM-module/" target="_blank">http://www.eetimes.com/electronics-news/4211854/Samsung-trials-DDR4-DRAM-module/</a> <a href="#fnref:15" class="footnote-back-ref">↩</a></p></li> <li id="fn:16"><p>"Intel Debuts 32-NM Westmere Desktop Processors" Archived 2010-03-17 at the Wayback Machine. InformationWeek. 7 January 2010. Retrieved 17 December 2011. <a href="http://www.informationweek.com/news/security/management/showArticle.jhtml?articleID=222200708" target="_blank">http://www.informationweek.com/news/security/management/showArticle.jhtml?articleID=222200708</a> <a href="#fnref:16" class="footnote-back-ref">↩</a></p></li> <li id="fn:17"><p>Sal Cangeloso (4 February 2010). "Intel's 6-core 32nm processors arriving soon". Geek.com. Archived from the original on 30 March 2012. Retrieved 11 November 2011. <a href="https://web.archive.org/web/20120330104041/http://www.geek.com/articles/chips/intels-6-core-32nm-processors-arriving-soon-2010024/" target="_blank">https://web.archive.org/web/20120330104041/http://www.geek.com/articles/chips/intels-6-core-32nm-processors-arriving-soon-2010024/</a> <a href="#fnref:17" class="footnote-back-ref">↩</a></p></li> <li id="fn:18"><p>"Intel's 10nm Cannon Lake and Core i3-8121U Deep Dive Review". <a href="https://www.anandtech.com/show/13405/intel-10nm-cannon-lake-and-core-i3-8121u-deep-dive-review/3" target="_blank">https://www.anandtech.com/show/13405/intel-10nm-cannon-lake-and-core-i3-8121u-deep-dive-review/3</a> <a href="#fnref:18" class="footnote-back-ref">↩</a></p></li> <li id="fn:19"><p>"Ambarella A7L Enables the Next Generation of Digital Still Cameras with 1080p60 Fluid Motion Video". Ambarella.com. 26 September 2011. Archived from the original on 10 November 2011. Retrieved 11 November 2011. <a href="https://web.archive.org/web/20111110054035/http://www.ambarella.com/news/26/74/Ambarella-A7L-Enables-the-Next-Generation-of-Digital-Still-Cameras-with-1080p60-Fluid-Motion-Video.html" target="_blank">https://web.archive.org/web/20111110054035/http://www.ambarella.com/news/26/74/Ambarella-A7L-Enables-the-Next-Generation-of-Digital-Still-Cameras-with-1080p60-Fluid-Motion-Video.html</a> <a href="#fnref:19" class="footnote-back-ref">↩</a></p></li> <li id="fn:20"><p>"Intel's CEO Discusses Q3 2011 Results - Earnings Call Transcript". Seeking Alpha. 18 October 2011. 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