Menu
Home
People
Places
Arts
History
Plants & Animals
Science
Life & Culture
Technology
Reference.org
Comparison of instruction set architectures
open-in-new
<h2 id="data-representation">Data representation</h2> <p>In the early decades of computing, there were computers that used <a href="/facts/Binary_number/a6JDSRPs">binary</a>, <a href="/facts/Decimal_computer/03q4eQAA">decimal</a><a class="footnote-ref" id="fnref:1" href="#fn:1"><sup>1</sup></a> and even <a href="/facts/Ternary_computer/tU1DI6wo">ternary</a>.<a class="footnote-ref" id="fnref:2" href="#fn:2"><sup>2</sup></a><a class="footnote-ref" id="fnref:3" href="#fn:3"><sup>3</sup></a> Contemporary computers are almost exclusively binary. </p><p>Characters are encoded as strings of bits or digits, using a wide variety of character sets; even within a single manufacturer there were character set differences. </p><p>Integers are encoded with a variety of <a href="/facts/Signed_number_representations/cE0sEMau">representations</a>, including <a href="/facts/Signed_number_representations/cE0sEMau">Sign-magnitude</a>, <a href="/facts/Signed_number_representations/cE0sEMau">Ones' complement</a>, <a href="/facts/Signed_number_representations/cE0sEMau">Two's complement</a>, <a href="/facts/Signed_number_representations/cE0sEMau">Offset binary</a>, <a href="/facts/Method_of_complements/1bWGERAk">Nines' complement</a> and <a href="/facts/Method_of_complements/1bWGERAk">Ten's complement</a>. </p><p>Similarly, floating point numbers are encoded with a variety of representations for the sign, <a href="/facts/Exponent/pac6QY2g">exponent</a> and <a href="/facts/Significand/JFCVyTz4">mantissa</a>. In contemporary machines <a href="/facts/IBM_hexadecimal_floating-point/EE3YS5aF">IBM hexadecimal floating-point</a> and <a href="/facts/IEEE_754/dD3e7zAl">IEEE 754</a> floating point have largely supplanted older formats. </p><p>Addresses are typically unsigned integers generated from a combination of fields in an instruction, data from registers and data from storage; the details vary depending on the architecture. </p> <h3>Bits</h3> <p><a href="/facts/Computer_architecture/tHtwxgR2">Computer architectures</a> are often described as <i>n</i>-<a href="/facts/Bit/RwfjaYSv">bit</a> architectures. In the first 3⁄4 of the 20th century, <i>n</i> is often <a href="/facts/12-bit_computing/6q6tqghX">12</a>, <a href="/facts/18-bit_computing/CgrYUIxM">18</a>, <a href="/facts/24-bit_computing/c7x41A13">24</a>, 30, <a href="/facts/36-bit_computing/P0V83YtM">36</a>, <a href="/facts/48-bit_computing/KTsN8bB1">48</a> or <a href="/facts/60-bit_computing/LL3TCIkV">60</a>. In the last 1⁄3 of the 20th century, <i>n</i> is often 8, 16, or 32, and in the 21st century, <i>n</i> is often 16, 32 or 64, but other sizes have been used (including 6, <a href="/facts/Elliott_803/m8TIrlxn">39</a>, <a href="/facts/128-bit_computing/fo1QpdNj">128</a>). This is actually a simplification as computer architecture often has a few more or less "natural" data sizes in the <a href="/facts/Instruction_set/8p8vwUeE">instruction set</a>, but the hardware implementation of these may be very different. Many instruction set architectures have instructions that, on some implementations of that instruction set architecture, operate on half and/or twice the size of the processor's major internal datapaths. Examples of this are the <a href="/facts/Z80/Jeqe2h55">Z80</a>, <a href="/facts/MC68000/3p2wt2D6">MC68000</a>, and the <a href="/facts/IBM_System%2f360/7znvpy4K">IBM System/360</a>. On these types of implementations, a twice as wide operation typically also takes around twice as many clock cycles (which is not the case on high performance implementations). On the 68000, for instance, this means 8 instead of 4 clock ticks, and this particular chip may be described as a <a href="/facts/32-bit_computing/TDMVce8s">32-bit</a> architecture with a <a href="/facts/16-bit_computing/bTGS44Ne">16-bit</a> implementation. The IBM System/360 instruction set architecture is 32-bit, but several models of the System/360 series, such as the <a href="/facts/IBM_System%2f360_Model_30/Jr2vfIjC">IBM System/360 Model 30</a>, have smaller internal data paths, while others, such as the <a href="/facts/360%2f195/mSrspKIg">360/195</a>, have larger internal data paths. The external databus width is not used to determine the width of the architecture; the <a href="/facts/NS320xx/zCXoyxzh">NS32008, NS32016 and NS32032</a> were basically the same 32-bit chip with different external data buses; the NS32764 had a <a href="/facts/64-bit_computing/AgvkQHkM">64-bit</a> bus, and used 32-bit register. Early 32-bit microprocessors often had a 24-bit address, as did the System/360 processors. </p> <h3>Digits</h3> <p>In the first 3⁄4 of the 20th century, word oriented decimal computers typically had 10 digit<a class="footnote-ref" id="fnref:4" href="#fn:4"><sup>4</sup></a><a class="footnote-ref" id="fnref:5" href="#fn:5"><sup>5</sup></a><a class="footnote-ref" id="fnref:6" href="#fn:6"><sup>6</sup></a> words with a separate sign,<a class="footnote-ref" id="fnref:7" href="#fn:7"><sup>7</sup></a> using all ten digits in integers and using two digits for exponents<a class="footnote-ref" id="fnref:8" href="#fn:8"><sup>8</sup></a><a class="footnote-ref" id="fnref:9" href="#fn:9"><sup>9</sup></a> in floating point numbers. </p> <h3>Endianness</h3> <p>An architecture may use "big" or "little" endianness, or both, or be configurable to use either. Little-endian processors order <a href="/facts/Byte/BNHUp9Qq">bytes</a> in memory with the least significant byte of a multi-byte value in the lowest-numbered memory location. Big-endian architectures instead arrange bytes with the most significant byte at the lowest-numbered address. The x86 architecture as well as several <a href="/facts/8-bit_computing/2CkhLNoH">8-bit</a> architectures are little-endian. Most <a href="/facts/RISC/aQbGM62p">RISC</a> architectures (SPARC, Power, PowerPC, MIPS) were originally big-endian (ARM was little-endian), but many (including ARM) are now configurable as either. </p><p>Endianness <i>only</i> applies to processors that allow individual addressing of units of data (such as <a href="/facts/Bytes/BNHUp9Qq">bytes</a>) that are <i>smaller</i> than some of the data formats. </p> <h2 id="instruction-formats">Instruction formats</h2> <h3>Opcodes</h3> <p>In some architectures, an instruction has a single opcode. In others, some instructions have an opcode and one or more modifiers. E.g., on the <a href="/facts/IBM_System%2f370/TRo1jaFw">IBM System/370</a>, byte 0 is the opcode but when byte 0 is a B216 then byte 1 selects a specific instruction, e.g., B20516 is store clock (STCK). </p> <h3>Operands</h3> <h4>Addressing modes</h4> <p class="note">Main article: <a href="/facts/Addressing_mode/g78wINgK">Addressing mode</a></p> <p>Architectures typically allow instructions to include some combination of operand <a href="/facts/Addressing_mode/g78wINgK">addressing modes</a>: </p> Direct The instruction specifies a complete address Immediate The instruction specifies a value rather than an address Indexed The instruction specifies a register to use as an index. In some architecture the index is scaled by the operand length. Indirect The instruction specifies the location of a pointer word that describes the operand, possibly involving multiple levels of indexing and indirection Truncated The instruction specifies the low order bits and a register provides the high order bits. Base-displacement The instruction specifies a displacement from an address in a register autoincrement/autodecrement A register used for indexing, or a pointer word used by indirect addressing, is incremented or decremented by 1, an operand size or an explicit delta <h4>Number of operands</h4> <p class="note">Main article: <a href="/facts/Instruction_set/8p8vwUeE">instruction set § Number of operands</a></p> <p>The number of operands is one of the factors that may give an indication about the performance of the instruction set. A three-operand architecture (2-in, 1-out) will allow </p> A := B + C <p>to be computed in one instruction </p> ADD B, C, A <p>A two-operand architecture (1-in, 1-in-and-out) will allow </p> A := A + B <p>to be computed in one instruction </p> ADD B, A <p>but requires that </p> A := B + C <p>be done in two instructions </p> MOVE B, A ADD C, A <h3>Encoding length</h3> <p>As can be seen in the table below some instructions sets keep to a very simple fixed encoding length, and other have variable-length. Usually it is <a href="/facts/RISC/aQbGM62p">RISC</a> architectures that have fixed encoding length and <a href="/facts/Complex_instruction_set_computer/Ucvyh2xq">CISC</a> architectures that have variable length, but not always. </p> <h2 id="instruction-sets">Instruction sets</h2> <p>The table below compares basic information about instruction set architectures. </p><p>Notes: </p> <ul><li>Usually the number of registers is a <a href="/facts/Power_of_two/MA6WEpTt">power of two</a>, e.g. 8, 16, 32. In some cases a hardwired-to-zero pseudo-register is included, as "part" of <a href="/facts/Register_file/NGvqUwe3">register files</a> of architectures, mostly to simplify indexing modes. The column "Registers" only counts the integer "registers" usable by general instructions at any moment. Architectures always include special-purpose registers such as the program counter (PC). Those are not counted unless mentioned. Note that some architectures, such as SPARC, have <a href="/facts/Register_window/RKBEPuAe">register windows</a>; for those architectures, the count indicates how many registers are available within a register window. Also, non-architected registers for <a href="/facts/Register_renaming/m1HXzC5x">register renaming</a> are not counted.</li> <li>In the "Type" column, "Register–Register" is a synonym for a common type of architecture, "<a href="/facts/Load%25E2%2580%2593store_architecture/nplXcr1B">load–store</a>", meaning that no instruction can directly access memory except some special ones, i.e. load to or store from register(s), with the possible exceptions of memory locking instructions for atomic operations.</li> <li>In the "Endianness" column, "Bi" means that the endianness is configurable.</li></ul> <table><tbody><tr><th>Architecture</th><th>Bits</th><th>Version</th><th>Introduced</th><th>Max #<a href="/facts/Operand/HSuUzrKz">operands</a></th><th>Type</th><th>Design</th><th><a href="/facts/Processor_register/32RvbUdz">Registers</a>(excluding FP/vector)</th><th>Instruction encoding</th><th><a href="/facts/Branch_(computer_science)/obBGrnor">Branch</a> evaluation</th><th><a href="/facts/Endianness/wbrQnyu3">Endianness</a></th><th>Extensions</th><th>Open</th><th>Royaltyfree</th></tr><tr><td><a href="/facts/MOS_Technology_6502/q9YLwkzm">6502</a></td><td>8</td><td></td><td>1975</td><td>1</td><td><a href="/facts/Register%25E2%2580%2593memory_architecture/w9fXBcrx">Register–Memory</a></td><td><a href="/facts/Complex_instruction_set_computer/Ucvyh2xq">CISC</a></td><td>3</td><td>Variable (8- to 24-bit)</td><td>Condition register</td><td>Little</td><td></td><td></td><td></td></tr><tr><td><a href="/facts/Motorola_6800/0D4BNIha">6800</a></td><td>8</td><td></td><td>1974</td><td>1</td><td>Register–Memory</td><td>CISC</td><td>3</td><td>Variable (8- to 24-bit)</td><td>Condition register</td><td>Big</td><td></td><td></td><td></td></tr><tr><td><a href="/facts/Motorola_6809/AM6UosAk">6809</a></td><td>8</td><td></td><td>1978</td><td>1</td><td>Register–Memory</td><td>CISC</td><td>4</td><td>Variable (8- to 32-bit)</td><td>Condition register</td><td>Big</td><td></td><td></td><td></td></tr><tr><td><a href="/facts/Motorola_68000_series/jxd7VPlW">680x0</a></td><td>32</td><td></td><td>1979</td><td>2</td><td>Register–Memory</td><td>CISC</td><td>8 data and 8 address</td><td>Variable</td><td>Condition register</td><td>Big</td><td></td><td></td><td></td></tr><tr><td><a href="/facts/8080/32FvNTcD">8080</a></td><td>8</td><td></td><td>1974</td><td>2</td><td>Register–Memory</td><td>CISC</td><td>7</td><td>Variable (8 to 24 bits)</td><td>Condition register</td><td>Little</td><td></td><td></td><td></td></tr><tr><td><a href="/facts/8051/2bqJXGlv">8051</a></td><td>32 (8→32)</td><td></td><td>1977?</td><td>1</td><td><a href="/facts/Load%25E2%2580%2593store_architecture/nplXcr1B">Register–Register</a></td><td>CISC</td><td><ul><li>32 in 4-bit</li><li>16 in 8-bit</li><li>8 in 16-bit</li><li>4 in 32-bit</li></ul></td><td>Variable (8 to 24 bits)</td><td>Compare and branch</td><td>Little</td><td></td><td></td><td></td></tr><tr><td><a href="/facts/X86/Kypq5fgu">x86</a></td><td>16, 32, 64(16→32→64)</td><td>v4 (x86-64)</td><td>1978</td><td>2 (integer)3 (<a href="/facts/Advanced_Vector_Extensions/znDpc6Vt">AVX</a>)<a class="footnote-ref" id="fnref:10" href="#fn:10"><sup>10</sup></a>4 (<a href="/facts/FMA_instruction_set/mqglSHqk">FMA4</a> and VPBLENDVPx)<a class="footnote-ref" id="fnref:11" href="#fn:11"><sup>11</sup></a></td><td>Register–Memory</td><td>CISC</td><td><ul><li>8 (+ 4 or 6 segment reg.) (16/32-bit)</li><li>16 (+ 2 segment reg. gs/cs) (64-bit)</li><li>32 with AVX-512 and Advance Performance eXtension (apx)</li></ul></td><td>Variable (8086 ~ 80386: variable between 1 and 6 bytes /w MMU + intel SDK, 80486: 2 to 5 bytes with prefix, pentium and onward: 2 to 4 bytes with prefix, x64: 4 bytes prefix, third party x86 emulation: 1 to 15 bytes w/o prefix & MMU . SSE/MMX: 4 bytes /w prefix AVX: 8 Bytes /w prefix)</td><td>Condition code</td><td>Little</td><td><a href="/facts/X87/y8X9HnLL">x87</a>, <a href="/facts/IA-32/7yTv1aHH">IA-32</a>, <a href="/facts/MMX_(instruction_set)/8o3JJhns">MMX</a>, <a href="/facts/3DNow!/QYJL2HBt">3DNow!</a>, <a href="/facts/Streaming_SIMD_Extensions/mMa6EFyB">SSE</a>,<a href="/facts/SSE2/cheNDPSK">SSE2</a>, <a href="/facts/Physical_Address_Extension/aEr4tj4x">PAE</a>, <a href="/facts/X86-64/cyWvUFlP">x86-64</a>, <a href="/facts/SSE3/Ch9oP4oh">SSE3</a>, <a href="/facts/SSSE3/xlRTcz4I">SSSE3</a>, <a href="/facts/SSE4/Tnxrl7Ph">SSE4</a>,<a href="/facts/Bit_Manipulation_Instruction_Sets/LJAm1LWC">BMI</a>, <a href="/facts/Advanced_Vector_Extensions/znDpc6Vt">AVX</a>, <a href="/facts/AES_instruction_set/NomFEB4w">AES</a>, <a href="/facts/FMA_instruction_set/mqglSHqk">FMA</a>, <a href="/facts/XOP_instruction_set/Xey2cAGM">XOP</a>, <a href="/facts/F16C/v6G70oa7">F16C</a>, <a href="/facts/Advanced_Matrix_Extensions/qkDBQbBE">AMX</a></td><td>No</td><td>No</td></tr><tr><td><a href="/facts/DEC_Alpha/4eN7LuXG">Alpha</a></td><td>64</td><td></td><td>1992</td><td>3</td><td>Register–Register</td><td><a href="/facts/Reduced_instruction_set_computer/aQbGM62p">RISC</a></td><td>32 (including "zero")</td><td>Fixed (32-bit)</td><td>Condition register</td><td>Bi</td><td>MVI, BWX, FIX, CIX</td><td>No</td><td></td></tr><tr><td><a href="/facts/ARC_(processor)/oFXJYBNR">ARC</a></td><td>16/32/64 (32→64)</td><td>ARCv3<a class="footnote-ref" id="fnref:12" href="#fn:12"><sup>12</sup></a></td><td>1996</td><td>3</td><td>Register–Register</td><td>RISC</td><td>16 or 32 including SP user can increase to 60</td><td>Variable (16- or 32-bit)</td><td>Compare and branch</td><td>Bi</td><td>APEX User-defined instructions</td><td></td><td></td></tr><tr><td><a href="/facts/ARM_architecture/SALsYA79">ARM/A32</a></td><td>32</td><td>ARMv1–v9</td><td>1983</td><td>3</td><td>Register–Register</td><td>RISC</td><td><ul><li>15</li></ul></td><td>Fixed (32-bit)</td><td>Condition code</td><td>Bi</td><td>NEON, <a href="/facts/Jazelle/CCA7g8wC">Jazelle</a>, VFP,<a href="/facts/TrustZone/SALsYA79">TrustZone</a>, LPAE</td><td></td><td>No</td></tr><tr><td><a href="/facts/ARM_architecture/SALsYA79">Thumb/T32</a></td><td>32</td><td>ARMv4T-ARMv8</td><td>1994</td><td>3</td><td>Register–Register</td><td>RISC</td><td><ul><li>7 with 16-bit Thumb instructions</li><li>15 with 32-bit Thumb-2 instructions</li></ul></td><td>Thumb: Fixed (16-bit), Thumb-2:Variable (16- or 32-bit)</td><td>Condition code</td><td>Bi</td><td>NEON, <a href="/facts/Jazelle/CCA7g8wC">Jazelle</a>, VFP,<a href="/facts/TrustZone/SALsYA79">TrustZone</a>, LPAE</td><td></td><td>No</td></tr><tr><td><a href="/facts/ARM_architecture/SALsYA79">Arm64/A64</a></td><td>64</td><td>v8.9-A/v9.4-A,<a class="footnote-ref" id="fnref:13" href="#fn:13"><sup>13</sup></a> Armv8-R<a class="footnote-ref" id="fnref:14" href="#fn:14"><sup>14</sup></a></td><td>2011<a class="footnote-ref" id="fnref:15" href="#fn:15"><sup>15</sup></a></td><td>3</td><td>Register–Register</td><td>RISC</td><td>32 (including the stack pointer/"zero" register)</td><td>Fixed (32-bit), Variable (32-bit or 64-bit for <a href="/facts/Fujitsu_A64FX/k5K0NoAt">FMA4</a> with 32-bit prefix<a class="footnote-ref" id="fnref:16" href="#fn:16"><sup>16</sup></a>)</td><td>Condition code</td><td>Bi</td><td>SVE and SVE2</td><td></td><td>No</td></tr><tr><td><a href="/facts/Atmel_AVR_instruction_set/UEv9ASzW">AVR</a></td><td>8</td><td></td><td>1997</td><td>2</td><td>Register–Register</td><td>RISC</td><td>3216 on "reduced architecture"</td><td>Variable (mostly 16-bit, four instructions are 32-bit)</td><td>Condition register,skip conditionedon an I/O orgeneral purposeregister bit,compare and skip</td><td>Little</td><td></td><td></td><td></td></tr><tr><td><a href="/facts/AVR32/h0rYkzpA">AVR32</a></td><td>32</td><td>Rev 2</td><td>2006</td><td>2–3</td><td></td><td>RISC</td><td>15</td><td>Variable<a class="footnote-ref" id="fnref:17" href="#fn:17"><sup>17</sup></a></td><td></td><td>Big</td><td><a href="/facts/Java_virtual_machine/l9Nzrsun">Java virtual machine</a></td><td></td><td></td></tr><tr><td><a href="/facts/Blackfin/9pc3fLf8">Blackfin</a></td><td>32</td><td></td><td>2000</td><td>3<a class="footnote-ref" id="fnref:18" href="#fn:18"><sup>18</sup></a></td><td>Register–Register</td><td>RISC<a class="footnote-ref" id="fnref:19" href="#fn:19"><sup>19</sup></a></td><td>2 accumulators<p>8 data registers</p><p>8 pointer registers</p><p>4 index registers</p><p>4 buffer registers</p></td><td>Variable (16- or 32-bit)</td><td>Condition code</td><td>Little<a class="footnote-ref" id="fnref:20" href="#fn:20"><sup>20</sup></a></td><td></td><td></td><td></td></tr><tr><td><a href="/facts/CDC_3600/s4DQdR7Y">CDC Upper 3000 series</a></td><td>48</td><td></td><td>1963</td><td>3</td><td>Register–Memory</td><td>CISC</td><td>48-bit A reg., 48-bit Q reg., 6 15-bit B registers, miscellaneous</td><td>Variable (24- or 48-bit)</td><td>Multiple types of jump and skip</td><td>Big</td><td></td><td></td><td></td></tr><tr><td><a href="/facts/CDC_6000_series/WDWo1psf">CDC 6000</a><a href="/facts/CDC_6600/QpnT1Ltl">Central Processor (CP)</a></td><td>60</td><td></td><td>1964</td><td>3</td><td>Register–Register</td><td>N/A<a class="footnote-ref" id="fnref:21" href="#fn:21"><sup>21</sup></a></td><td>24 (8 18-bit address reg.,8 18-bit index reg.,8 60-bit operand reg.)</td><td>Variable (15-, 30-, or 60-bit)</td><td>Compare and branch</td><td>N/A<a class="footnote-ref" id="fnref:22" href="#fn:22"><sup>22</sup></a></td><td>Compare/Move Unit</td><td>No</td><td>No</td></tr><tr><td><a href="/facts/CDC_6000_series/WDWo1psf">CDC 6000</a><a href="/facts/CDC_6600/QpnT1Ltl">Peripheral Processor (PP)</a></td><td>12</td><td></td><td>1964</td><td>1 or 2</td><td>Register–Memory</td><td>CISC</td><td>1 18-bit A register, locations 1–63 serve as index registers for some instructions</td><td>Variable (12- or 24-bit)</td><td>Test A register, test channel</td><td>N/A<a class="footnote-ref" id="fnref:23" href="#fn:23"><sup>23</sup></a></td><td>additional Peripheral Processing Units</td><td>No</td><td>No</td></tr><tr><td><a href="/facts/Transmeta_Crusoe/gHy6WQRg">Crusoe</a>(native VLIW)</td><td>32<a class="footnote-ref" id="fnref:24" href="#fn:24"><sup>24</sup></a></td><td></td><td>2000</td><td>1</td><td>Register–Register</td><td><a href="/facts/Very_long_instruction_word/WJuzewyR">VLIW</a><a class="footnote-ref" id="fnref:25" href="#fn:25"><sup>25</sup></a><a class="footnote-ref" id="fnref:26" href="#fn:26"><sup>26</sup></a></td><td><ul><li>1 in native push stack mode</li><li>6 in x86 emulation +8 in x87/MMX mode +50 in rename status</li><li>12 integer + 48 shadow +4 debug in native VLIW</li><li>mode<a class="footnote-ref" id="fnref:27" href="#fn:27"><sup>27</sup></a><a class="footnote-ref" id="fnref:28" href="#fn:28"><sup>28</sup></a></li></ul></td><td>Variable (64- or 128-bit in native mode, 15 bytes in x86 emulation)<a class="footnote-ref" id="fnref:29" href="#fn:29"><sup>29</sup></a></td><td>Condition code<a class="footnote-ref" id="fnref:30" href="#fn:30"><sup>30</sup></a></td><td>Little</td><td></td><td></td><td></td></tr><tr><td><a href="/facts/Elbrus_2000/uCUJ7r0x">Elbrus 2000</a>(native VLIW)</td><td>64</td><td>v6</td><td>2007</td><td>1</td><td>Register–Register<a class="footnote-ref" id="fnref:31" href="#fn:31"><sup>31</sup></a></td><td>VLIW</td><td>8–64</td><td>64</td><td>Condition code</td><td>Little</td><td>Just-in-time dynamic translation: <a href="/facts/X87/y8X9HnLL">x87</a>, <a href="/facts/IA-32/7yTv1aHH">IA-32</a>, <a href="/facts/MMX_(instruction_set)/8o3JJhns">MMX</a>, <a href="/facts/Streaming_SIMD_Extensions/mMa6EFyB">SSE</a>,<a href="/facts/SSE2/cheNDPSK">SSE2</a>, <a href="/facts/X86-64/cyWvUFlP">x86-64</a>, <a href="/facts/SSE3/Ch9oP4oh">SSE3</a>, <a href="/facts/Advanced_Vector_Extensions/znDpc6Vt">AVX</a></td><td>No</td><td>No</td></tr><tr><td><a href="/facts/DLX/ehqMj5Kh">DLX</a></td><td>32</td><td>?</td><td>1990</td><td>3</td><td>Register–Register</td><td>RISC</td><td>32</td><td>Fixed (32-bit)</td><td>Condition register</td><td>Big</td><td>?</td><td>Yes</td><td>?</td></tr><tr><td><a href="/facts/ESi-RISC/78jTInNd">eSi-RISC</a></td><td>16/32</td><td></td><td>2009</td><td>3</td><td>Register–Register</td><td>RISC</td><td>8–72</td><td>Variable (16- or 32-bit)</td><td>Compare and branchand condition register</td><td>Bi</td><td>User-defined instructions</td><td>No</td><td>No</td></tr><tr><td><a href="/facts/Intel_iAPX_432/z0xPqFQf">iAPX 432</a><a class="footnote-ref" id="fnref:32" href="#fn:32"><sup>32</sup></a></td><td>32</td><td></td><td>1981</td><td>3</td><td><a href="/facts/Stack_machine/IBtk4NRA">Stack machine</a></td><td>CISC</td><td>0</td><td>Variable (6 to 321 bits)</td><td></td><td></td><td></td><td>No</td><td>No</td></tr><tr><td><a href="/facts/Itanium/0wkjSDpe">Itanium</a>(IA-64)</td><td>64</td><td></td><td>2001</td><td></td><td>Register–Register</td><td><a href="/facts/Explicitly_parallel_instruction_computing/H5tD9TRg">EPIC</a></td><td>128</td><td>Fixed (128-bit bundles with 5-bit template tag and 3 instructions, each 41-bit long)</td><td>Condition register</td><td>Bi(selectable)</td><td>Intel Virtualization Technology</td><td>No</td><td>No</td></tr><tr><td><a href="/facts/Loongson/6AhDhaeU">LoongArch</a></td><td>32, 64</td><td></td><td>2021</td><td>4</td><td>Register–Register</td><td>RISC</td><td>32 (including "zero")</td><td>Fixed (32-bit)</td><td></td><td>Little</td><td></td><td>No</td><td>No</td></tr><tr><td><a href="/facts/M32R/SztNrULr">M32R</a></td><td>32</td><td></td><td>1997</td><td>3</td><td>Register–Register</td><td>RISC</td><td>16</td><td>Variable (16- or 32-bit)</td><td>Condition register</td><td>Bi</td><td></td><td></td><td></td></tr><tr><td><a href="/facts/Motorola_88000/7GfVFIWo">m88k</a></td><td>32</td><td></td><td>1988</td><td>3</td><td>Register–Register</td><td>RISC</td><td>32</td><td>Fixed (32-bit)</td><td>Compare and branch</td><td>Big</td><td></td><td></td><td></td></tr><tr><td><a href="/facts/LatticeMico32/5KXwoTol">Mico32</a></td><td>32</td><td>?</td><td>2006</td><td>3</td><td>Register–Register</td><td>RISC</td><td>32<a class="footnote-ref" id="fnref:33" href="#fn:33"><sup>33</sup></a></td><td>Fixed (32-bit)</td><td>Compare and branch</td><td>Big</td><td>User-defined instructions</td><td>Yes<a class="footnote-ref" id="fnref:34" href="#fn:34"><sup>34</sup></a></td><td>Yes</td></tr><tr><td><a href="/facts/MIPS_architecture/efV4KgK4">MIPS</a></td><td>64 (32→64)</td><td>6<a class="footnote-ref" id="fnref:35" href="#fn:35"><sup>35</sup></a><a class="footnote-ref" id="fnref:36" href="#fn:36"><sup>36</sup></a></td><td>1981</td><td>1–3</td><td>Register–Register</td><td>RISC</td><td>4–32 (including "zero")</td><td>Fixed (32-bit)</td><td>Condition register</td><td>Bi</td><td><a href="/facts/MDMX/fI3opPDQ">MDMX</a>, <a href="/facts/MIPS-3D/moHaD8sY">MIPS-3D</a></td><td>No</td><td>No<a class="footnote-ref" id="fnref:37" href="#fn:37"><sup>37</sup></a><a class="footnote-ref" id="fnref:38" href="#fn:38"><sup>38</sup></a></td></tr><tr><td><a href="/facts/MMIX/ttL2sAbM">MMIX</a></td><td>64</td><td>?</td><td>1999</td><td>3</td><td>Register–Register</td><td>RISC</td><td>256</td><td>Fixed (32-bit)</td><td>Condition register</td><td>Big</td><td>?</td><td>Yes</td><td>Yes</td></tr><tr><td><a href="/facts/Nios_II/sbFl05Wx">Nios II</a></td><td>32</td><td>?</td><td>2000</td><td>3</td><td>Register–Register</td><td>RISC</td><td>32</td><td>Fixed (32-bit)</td><td>Condition register</td><td>Little</td><td>Soft processor that can be instantiated on an Altera FPGA device</td><td>No</td><td>On Altera/Intel FPGA only</td></tr><tr><td><a href="/facts/Data_General_Nova/z4YhpLuD">Nova</a></td><td>16</td><td></td><td>1969</td><td>2</td><td>Register–Register</td><td>CISC</td><td>4</td><td>Fixed (16-bit)</td><td>Skip</td><td>None</td><td></td><td></td><td></td></tr><tr><td><a href="/facts/NS320xx/zCXoyxzh">NS320xx</a></td><td>32</td><td></td><td>1982</td><td>5</td><td>Memory–Memory</td><td>CISC</td><td>8</td><td>Variable <a href="/facts/Huffman_coding/dBgMBz48">Huffman coded</a>, up to 23 bytes long</td><td>Condition code</td><td>Little</td><td>BitBlt instructions</td><td></td><td></td></tr><tr><td><a href="/facts/OpenRISC/G40wlEKP">OpenRISC</a></td><td>32, 64</td><td>1.4<a class="footnote-ref" id="fnref:39" href="#fn:39"><sup>39</sup></a></td><td>2000</td><td>3</td><td>Register–Register</td><td>RISC</td><td>16 or 32</td><td>Fixed</td><td>Condition code</td><td>Bi</td><td>?</td><td>Yes</td><td>Yes</td></tr><tr><td><a href="/facts/PA-RISC/gjDs1HEh">PA-RISC</a>(HP/PA)</td><td>64 (32→64)</td><td>2.0</td><td>1986</td><td>3</td><td>Register–Register</td><td>RISC</td><td>32</td><td>Fixed (32-bit)</td><td>Compare and branch</td><td>Big → Bi</td><td><a href="/facts/Multimedia_Acceleration_eXtensions/sAIMJ4NI">MAX</a></td><td>No</td><td></td></tr><tr><td><a href="/facts/PDP-5/M5so7eEP">PDP-5</a><a class="footnote-ref" id="fnref:40" href="#fn:40"><sup>40</sup></a> <a href="/facts/PDP-8/udvrynE8">PDP-8</a><a class="footnote-ref" id="fnref:41" href="#fn:41"><sup>41</sup></a></td><td>12</td><td></td><td>1963</td><td></td><td>Register–Memory</td><td>CISC</td><td>1 accumulator<p>1 multiplier quotient register </p></td><td>Fixed (12-bit)</td><td>Condition register<p>Test and branch</p></td><td></td><td>EAE (Extended Arithmetic Element)</td><td></td><td></td></tr><tr><td><a href="/facts/PDP-11/9HkGUzFn">PDP-11</a></td><td>16</td><td></td><td>1970</td><td>2</td><td>Memory–Memory</td><td>CISC</td><td>8 (includes program counter and stack pointer, though any register can act as stack pointer)</td><td>Variable (16-, 32-, or 48-bit)</td><td>Condition code</td><td>Little</td><td>Extended Instruction Set, Floating Instruction Set, Floating Point Processor, Commercial Instruction Set</td><td>No</td><td>No</td></tr><tr><td><a href="/facts/IBM_POWER_instruction_set_architecture/AptQ0xLu">POWER</a>, <a href="/facts/PowerPC/DqmM9y50">PowerPC</a>, <a href="/facts/Power_ISA/GLy1WS0m">Power ISA</a></td><td>32/64 (32→64)</td><td>3.1<a class="footnote-ref" id="fnref:42" href="#fn:42"><sup>42</sup></a></td><td>1990</td><td>3 (mostly). FMA, LD/ST-Update</td><td>Register–Register</td><td>RISC</td><td>32 GPR, 8 4-bit Condition Fields, Link Register, Counter Register</td><td>Fixed (32-bit), Variable (32- or 64-bit with the 32-bit prefix<a class="footnote-ref" id="fnref:43" href="#fn:43"><sup>43</sup></a>)</td><td>Condition code, Branch-Counter auto-decrement</td><td>Bi</td><td><a href="/facts/AltiVec/Vn1DY71U">AltiVec</a>, APU, <a href="/facts/AltiVec/Vn1DY71U">VSX</a>, <a href="/facts/Cell_(microprocessor)/p2MIQjMc">Cell</a>, Floating-point, Matrix Multiply Assist</td><td>Yes</td><td>Yes</td></tr><tr><td><a href="/facts/RISC-V/pUSKDat1">RISC-V</a></td><td>32, 64, 128</td><td>20191213<a class="footnote-ref" id="fnref:44" href="#fn:44"><sup>44</sup></a></td><td>2010</td><td>3</td><td>Register–Register</td><td>RISC</td><td>32 (including "zero")</td><td>Variable</td><td>Compare and branch</td><td>Little</td><td>?</td><td>Yes</td><td>Yes</td></tr><tr><td><a href="/facts/RX_microcontroller_family/ujhb9Dcz">RX</a></td><td>64/32/16</td><td></td><td>2000</td><td>3</td><td>Memory–Memory</td><td>CISC</td><td>4 integer + 4 address</td><td>Variable</td><td>Compare and branch</td><td>Little</td><td></td><td></td><td>No</td></tr><tr><td><a href="/facts/S%252Bcore/gjINs0EU">S+core</a></td><td>16/32</td><td></td><td>2005</td><td></td><td></td><td>RISC</td><td></td><td></td><td></td><td>Little</td><td></td><td></td><td></td></tr><tr><td><a href="/facts/SPARC/m7KhEtET">SPARC</a></td><td>64 (32→64)</td><td>OSA2017<a class="footnote-ref" id="fnref:45" href="#fn:45"><sup>45</sup></a></td><td>1985</td><td>3</td><td>Register–Register</td><td>RISC</td><td>32 (including "zero")</td><td>Fixed (32-bit)</td><td>Condition code</td><td>Big → Bi</td><td><a href="/facts/Visual_Instruction_Set/9aTAKj2D">VIS</a></td><td>Yes</td><td>Yes<a class="footnote-ref" id="fnref:46" href="#fn:46"><sup>46</sup></a></td></tr><tr><td><a href="/facts/SuperH/4GTLXc1N">SuperH</a> (SH)</td><td>32</td><td>?</td><td>1994</td><td>2</td><td>Register–Register Register–Memory</td><td>RISC</td><td>16</td><td>Fixed (16- or 32-bit), Variable</td><td>Condition code(single bit)</td><td>Bi</td><td>?</td><td>Yes</td><td>Yes</td></tr><tr><td><a href="/facts/IBM_System%2f360_architecture/mKdceH2S">System/360</a><a href="/facts/System%2f370/TRo1jaFw">System/370</a><a href="/facts/System%2f390/lzkp2UE5">System/390</a><a href="/facts/Z%2fArchitecture/FcKYkGn9">z/Architecture</a></td><td>64 (32→64)</td><td></td><td>1964</td><td>2 (most)3 (FMA, distinctoperand facility)4 (some vector inst.)</td><td>Register–MemoryMemory–Memory Register–Register</td><td>CISC</td><td>16 general16 control (S/370 and later)16 access (ESA/370 and later)32 vector registers (z13 and later)</td><td>Variable (16-, 32-, or 48-bit)</td><td>Condition code, compare and branch [auto increment], Branch-Counter auto-decrement</td><td>Big</td><td></td><td>No</td><td>No</td></tr><tr><td><a href="/facts/TMS320/ILsPTHCJ">TMS320</a> C6000 series</td><td>32</td><td></td><td>1983</td><td>3</td><td>Register-Register</td><td>VLIW</td><td>32 on C67x 64 on C67x+</td><td>Fixed (256-bit bundles with 8 instructions, each 32-bit long)</td><td>Condition register</td><td>Bi</td><td></td><td>No</td><td>No</td></tr><tr><td><a href="/facts/Transputer/V0ShkUhE">Transputer</a></td><td>32 (4→64)</td><td></td><td>1987</td><td>1</td><td><a href="/facts/Stack_machine/IBtk4NRA">Stack machine</a></td><td><a href="/facts/Minimal_instruction_set_computer/KKjNJ4ff">MISC</a></td><td>3 (as stack)</td><td>Fixed (8-bit)</td><td>Compare and branch</td><td>Little</td><td></td><td></td><td></td></tr><tr><td><a href="/facts/VAX/N3r13IHH">VAX</a></td><td>32</td><td></td><td>1977</td><td>6</td><td>Memory–Memory</td><td>CISC</td><td>16</td><td>Variable</td><td>Condition code, compare and branch</td><td>Little</td><td></td><td>No</td><td></td></tr><tr><td><a href="/facts/Z80/Jeqe2h55">Z80</a></td><td>8</td><td></td><td>1976</td><td>2</td><td>Register–Memory</td><td>CISC</td><td>17</td><td>Variable (8 to 32 bits)</td><td>Condition register</td><td>Little</td><td></td><td></td><td></td></tr></tbody></table> <h2 id="see-also">See also</h2> <ul><li><a href="/facts/Central_processing_unit/Jxp1bqMV">Central processing unit</a> (CPU)</li> <li><a href="/facts/Processor_design/HeNbj78g">Processor design</a></li> <li><a href="/facts/Comparison_of_CPU_microarchitectures/l4fQNJCB">Comparison of CPU microarchitectures</a></li> <li><a href="/facts/Instruction_set_architecture/8p8vwUeE">Instruction set architecture</a></li> <li><a href="/facts/Microprocessor/Fx9CaQht">Microprocessor</a></li> <li><a href="/facts/Benchmark_(computing)/XSS42cRe">Benchmark (computing)</a></li></ul> <h2 id="notes">Notes</h2> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>da Cruz, Frank (October 18, 2004). "The IBM Naval Ordnance Research Calculator". Columbia University Computing History. Retrieved May 8, 2024. <a href="https://www.columbia.edu/cu/computinghistory/norc.html" target="_blank">https://www.columbia.edu/cu/computinghistory/norc.html</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>"Russian Virtual Computer Museum _ Hall of Fame _ Nikolay Petrovich Brusentsov". <a href="http://www.computer-museum.ru/english/galglory_en/Brusentsov.htm" target="_blank">http://www.computer-museum.ru/english/galglory_en/Brusentsov.htm</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li> <li id="fn:3"><p>Trogemann, Georg; Nitussov, Alexander Y.; Ernst, Wolfgang (2001). Computing in Russia: the history of computer devices and information technology revealed. Vieweg+Teubner Verlag. pp. 19, 55, 57, 91, 104–107. ISBN 978-3-528-05757-2.. <a href="978-3-528-05757-2" target="_blank">978-3-528-05757-2</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li> <li id="fn:4"><p>650 magnetic drum data processing machine (PDF). IBM. June 1955. 22-6060-2. Retrieved May 8, 2024. <a href="http://bitsavers.org/pdf/ibm/650/22-6060-2_650_OperMan.pdf" target="_blank">http://bitsavers.org/pdf/ibm/650/22-6060-2_650_OperMan.pdf</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li> <li id="fn:5"><p>IBM 7070-7074 Principles of Operation (PDF). Systems Reference Library. IBM. 1962. GA22-7003-6. Retrieved May 8, 2024. <a href="http://bitsavers.org/pdf/ibm/7070/GA22-7003-6_7070-7074prcOps.pdf" target="_blank">http://bitsavers.org/pdf/ibm/7070/GA22-7003-6_7070-7074prcOps.pdf</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></p></li> <li id="fn:6"><p>UNIVAC® Solid-state 80 Computer (PDF). Sperry Rand Corporation. 1959. U1742.1r3. Retrieved May 8, 2024. <a href="http://bitsavers.org/pdf/univac/uss/U1742.1r3_UNIVAC_Solid-State_80_General_Description_1959.pdf" target="_blank">http://bitsavers.org/pdf/univac/uss/U1742.1r3_UNIVAC_Solid-State_80_General_Description_1959.pdf</a> <a href="#fnref:6" class="footnote-back-ref">↩</a></p></li> <li id="fn:7"><p>Normally the sign could only be plus or minus, but on the IBM 7070/72/74[5] there was a 3-state sign. <a href="#fnref:7" class="footnote-back-ref">↩</a></p></li> <li id="fn:8"><p>IBM 650 MDDPM Additional Features - Indexing Accumulators - Floating-Decimal Arithmetic - Advanced Write-Up (PDF). IBM. 1955. 22-6258-0. Retrieved May 8, 2024. <a href="http://bitsavers.org/pdf/ibm/650/22-6258-0_FeaturesIdxAccum.pdf" target="_blank">http://bitsavers.org/pdf/ibm/650/22-6258-0_FeaturesIdxAccum.pdf</a> <a href="#fnref:8" class="footnote-back-ref">↩</a></p></li> <li id="fn:9"><p>IBM 7070-7074 Principles of Operation (PDF). Systems Reference Library. IBM. 1962. GA22-7003-6. Retrieved May 8, 2024. <a href="http://bitsavers.org/pdf/ibm/7070/GA22-7003-6_7070-7074prcOps.pdf" target="_blank">http://bitsavers.org/pdf/ibm/7070/GA22-7003-6_7070-7074prcOps.pdf</a> <a href="#fnref:9" class="footnote-back-ref">↩</a></p></li> <li id="fn:10"><p>The LEA (all processors) and IMUL-immediate (80186 & later) instructions accept three operands; most other instructions of the base integer ISA accept no more than two operands. <a href="#fnref:10" class="footnote-back-ref">↩</a></p></li> <li id="fn:11"><p>"AMD64 Architecture Programmer's Manual Volume 6: 128-Bit and 256-Bit XOP and FMA4 Instructions" (PDF). AMD. November 2009. <a href="https://www.amd.com/system/files/TechDocs/43479.pdf" target="_blank">https://www.amd.com/system/files/TechDocs/43479.pdf</a> <a href="#fnref:11" class="footnote-back-ref">↩</a></p></li> <li id="fn:12"><p>"Synopsys Introduces New 64-bit ARC Processor IP Delivering up to 3x Performance Increase for High-End Embedded Applications". <a href="https://news.synopsys.com/2020-04-07-Synopsys-Introduces-New-64-bit-ARC-Processor-IP-Delivering-Up-to-3x-Performance-Increase-for-High-End-Embedded-Applications" target="_blank">https://news.synopsys.com/2020-04-07-Synopsys-Introduces-New-64-bit-ARC-Processor-IP-Delivering-Up-to-3x-Performance-Increase-for-High-End-Embedded-Applications</a> <a href="#fnref:12" class="footnote-back-ref">↩</a></p></li> <li id="fn:13"><p>"Arm A-Profile Architecture Developments 2022 - Architectures and Processors blog - Arm Community blogs - Arm Community". community.arm.com. 29 September 2022. Retrieved 2022-12-09. <a href="https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-2022" target="_blank">https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-2022</a> <a href="#fnref:13" class="footnote-back-ref">↩</a></p></li> <li id="fn:14"><p>Frumusanu, Andrei (September 3, 2020). "ARM Announced Cortex-R82: First 64-bit Real Time Processor". AnandTech. <a href="https://www.anandtech.com/show/16056/arm-announces-cortexr82-first-64bit-real-time-processor" target="_blank">https://www.anandtech.com/show/16056/arm-announces-cortexr82-first-64bit-real-time-processor</a> <a href="#fnref:14" class="footnote-back-ref">↩</a></p></li> <li id="fn:15"><p>"ARM goes 64-bit with new ARMv8 chip architecture". Computerworld. 27 October 2011. Retrieved 8 May 2024. <a href="https://www.computerworld.com/article/1536136/arm-goes-64-bit-with-new-armv8-chip-architecture.html" target="_blank">https://www.computerworld.com/article/1536136/arm-goes-64-bit-with-new-armv8-chip-architecture.html</a> <a href="#fnref:15" class="footnote-back-ref">↩</a></p></li> <li id="fn:16"><p>Toshio Yoshida. "Hot Chips 30 conference; Fujitsu briefing" (PDF). Fujitsu. Archived from the original (PDF) on 2020-12-05. <a href="https://web.archive.org/web/20201205202434/https://hotchips.org/hc30/2conf/2.13_Fujitsu_HC30.Fujitsu.Yoshida.rev1.2.pdf" target="_blank">https://web.archive.org/web/20201205202434/https://hotchips.org/hc30/2conf/2.13_Fujitsu_HC30.Fujitsu.Yoshida.rev1.2.pdf</a> <a href="#fnref:16" class="footnote-back-ref">↩</a></p></li> <li id="fn:17"><p>"AVR32 Architecture Document" (PDF). Atmel. Retrieved 2024-05-08. <a href="https://ww1.microchip.com/downloads/en/devicedoc/doc32000.pdf" target="_blank">https://ww1.microchip.com/downloads/en/devicedoc/doc32000.pdf</a> <a href="#fnref:17" class="footnote-back-ref">↩</a></p></li> <li id="fn:18"><p>"Blackfin manual" (PDF). analog.com. <a href="https://www.analog.com/media/en/dsp-documentation/processor-manuals/blackfin_pgr_rev2.2.pdf" target="_blank">https://www.analog.com/media/en/dsp-documentation/processor-manuals/blackfin_pgr_rev2.2.pdf</a> <a href="#fnref:18" class="footnote-back-ref">↩</a></p></li> <li id="fn:19"><p>"Blackfin Processor Architecture Overview". Analog Devices. Retrieved 2024-05-08. <a href="https://www.analog.com/en/lp/001/blackfin-architecture.html" target="_blank">https://www.analog.com/en/lp/001/blackfin-architecture.html</a> <a href="#fnref:19" class="footnote-back-ref">↩</a></p></li> <li id="fn:20"><p>"Blackfin memory architecture". Analog Devices. Archived from the original on 2011-06-16. Retrieved 2009-12-18. <a href="https://web.archive.org/web/20110616182409/http://www.analog.com/FAQs/FAQDisplay.html?DSPKBContentID=752A11D1-9E11-4A7F-91AC-CA3C264C5667" target="_blank">https://web.archive.org/web/20110616182409/http://www.analog.com/FAQs/FAQDisplay.html?DSPKBContentID=752A11D1-9E11-4A7F-91AC-CA3C264C5667</a> <a href="#fnref:20" class="footnote-back-ref">↩</a></p></li> <li id="fn:21"><p>partly RISC: load/store architecture and simple addressing modes, partly CISC: three instruction lengths and no single instruction timing <a href="#fnref:21" class="footnote-back-ref">↩</a></p></li> <li id="fn:22"><p>Since memory is an array of 60-bit words with no means to access sub-units, big endian vs. little endian makes no sense. The optional CMU unit uses big-endian semantics. <a href="#fnref:22" class="footnote-back-ref">↩</a></p></li> <li id="fn:23"><p>Since memory is an array of 12-bit words with no means to access sub-units, big endian vs. little endian makes no sense. <a href="#fnref:23" class="footnote-back-ref">↩</a></p></li> <li id="fn:24"><p>"Crusoe Exposed: Transmeta TM5xxx Architecture 2". Real World Technologies. <a href="http://www.realworldtech.com/crusoe-exposed/" target="_blank">http://www.realworldtech.com/crusoe-exposed/</a> <a href="#fnref:24" class="footnote-back-ref">↩</a></p></li> <li id="fn:25"><p>"Crusoe Exposed: Transmeta TM5xxx Architecture 2". Real World Technologies. <a href="http://www.realworldtech.com/crusoe-exposed/" target="_blank">http://www.realworldtech.com/crusoe-exposed/</a> <a href="#fnref:25" class="footnote-back-ref">↩</a></p></li> <li id="fn:26"><p>Alexander Klaiber (January 2000). "The Technology Behind Crusoe Processors" (PDF). Transmeta Corporation. Retrieved December 6, 2013. <a href="http://www.cs.ucf.edu/~lboloni/Teaching/EEL5708_2004/slides/paper_aklaiber_19jan00.pdf" target="_blank">http://www.cs.ucf.edu/~lboloni/Teaching/EEL5708_2004/slides/paper_aklaiber_19jan00.pdf</a> <a href="#fnref:26" class="footnote-back-ref">↩</a></p></li> <li id="fn:27"><p>"Crusoe Exposed: Transmeta TM5xxx Architecture 2". Real World Technologies. <a href="http://www.realworldtech.com/crusoe-exposed/" target="_blank">http://www.realworldtech.com/crusoe-exposed/</a> <a href="#fnref:27" class="footnote-back-ref">↩</a></p></li> <li id="fn:28"><p>Alexander Klaiber (January 2000). "The Technology Behind Crusoe Processors" (PDF). Transmeta Corporation. Retrieved December 6, 2013. <a href="http://www.cs.ucf.edu/~lboloni/Teaching/EEL5708_2004/slides/paper_aklaiber_19jan00.pdf" target="_blank">http://www.cs.ucf.edu/~lboloni/Teaching/EEL5708_2004/slides/paper_aklaiber_19jan00.pdf</a> <a href="#fnref:28" class="footnote-back-ref">↩</a></p></li> <li id="fn:29"><p>Alexander Klaiber (January 2000). "The Technology Behind Crusoe Processors" (PDF). Transmeta Corporation. Retrieved December 6, 2013. <a href="http://www.cs.ucf.edu/~lboloni/Teaching/EEL5708_2004/slides/paper_aklaiber_19jan00.pdf" target="_blank">http://www.cs.ucf.edu/~lboloni/Teaching/EEL5708_2004/slides/paper_aklaiber_19jan00.pdf</a> <a href="#fnref:29" class="footnote-back-ref">↩</a></p></li> <li id="fn:30"><p>"Crusoe Exposed: Transmeta TM5xxx Architecture 2". Real World Technologies. <a href="http://www.realworldtech.com/crusoe-exposed/" target="_blank">http://www.realworldtech.com/crusoe-exposed/</a> <a href="#fnref:30" class="footnote-back-ref">↩</a></p></li> <li id="fn:31"><p>"Crusoe Exposed: Transmeta TM5xxx Architecture 2". Real World Technologies. <a href="http://www.realworldtech.com/crusoe-exposed/" target="_blank">http://www.realworldtech.com/crusoe-exposed/</a> <a href="#fnref:31" class="footnote-back-ref">↩</a></p></li> <li id="fn:32"><p>Intel Corporation (1981). Introduction to the iAPX 432 Architecture (PDF). pp. iii. <a href="http://bitsavers.org/components/intel/iAPX_432/171821-001_Introduction_to_the_iAPX_432_Architecture_Aug81.pdf" target="_blank">http://bitsavers.org/components/intel/iAPX_432/171821-001_Introduction_to_the_iAPX_432_Architecture_Aug81.pdf</a> <a href="#fnref:32" class="footnote-back-ref">↩</a></p></li> <li id="fn:33"><p>"LatticeMico32 Architecture". Lattice Semiconductor. Archived from the original on 23 June 2010. <a href="https://web.archive.org/web/20100623021729/http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/mico32architecture.cfm" target="_blank">https://web.archive.org/web/20100623021729/http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/mico32architecture.cfm</a> <a href="#fnref:33" class="footnote-back-ref">↩</a></p></li> <li id="fn:34"><p>"LatticeMico32 Open Source Licensing". Lattice Semiconductor. Archived from the original on 20 June 2010. <a href="https://web.archive.org/web/20100620185845/http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/mico32opensourcelicensing.cfm" target="_blank">https://web.archive.org/web/20100620185845/http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/mico32opensourcelicensing.cfm</a> <a href="#fnref:34" class="footnote-back-ref">↩</a></p></li> <li id="fn:35"><p>MIPS64 Architecture for Programmers: Release 6 <a href="https://www.mips.com/products/architectures/mips64/" target="_blank">https://www.mips.com/products/architectures/mips64/</a> <a href="#fnref:35" class="footnote-back-ref">↩</a></p></li> <li id="fn:36"><p>MIPS32 Architecture for Programmers: Release 6 <a href="https://www.mips.com/products/architectures/mips32-2/" target="_blank">https://www.mips.com/products/architectures/mips32-2/</a> <a href="#fnref:36" class="footnote-back-ref">↩</a></p></li> <li id="fn:37"><p>MIPS Open <a href="https://www.mipsopen.com/" target="_blank">https://www.mipsopen.com/</a> <a href="#fnref:37" class="footnote-back-ref">↩</a></p></li> <li id="fn:38"><p>"Wave Computing Closes Its MIPS Open Initiative with Immediate Effect, Zero Warning". <a href="https://www.hackster.io/news/wave-computing-closes-its-mips-open-initiative-with-immediate-effect-zero-warning-e88b0df9acd0" target="_blank">https://www.hackster.io/news/wave-computing-closes-its-mips-open-initiative-with-immediate-effect-zero-warning-e88b0df9acd0</a> <a href="#fnref:38" class="footnote-back-ref">↩</a></p></li> <li id="fn:39"><p>OpenRISC Architecture Revisions <a href="https://openrisc.io/architecture" target="_blank">https://openrisc.io/architecture</a> <a href="#fnref:39" class="footnote-back-ref">↩</a></p></li> <li id="fn:40"><p>PDP-5 Handbook (PDF). Digital Equipment Corporation. February 1964. <a href="http://www.bitsavers.org/pdf/dec/pdp5/F-55_PDP5Handbook_Feb64.pdf" target="_blank">http://www.bitsavers.org/pdf/dec/pdp5/F-55_PDP5Handbook_Feb64.pdf</a> <a href="#fnref:40" class="footnote-back-ref">↩</a></p></li> <li id="fn:41"><p>PDP-8 Users Handbook (PDF). Digital Equipment Corporation. May 1966. <a href="http://www.bitsavers.org/pdf/dec/pdp8/pdp8/F-85_PDP-8_Users_Handbook_May66.pdf" target="_blank">http://www.bitsavers.org/pdf/dec/pdp8/pdp8/F-85_PDP-8_Users_Handbook_May66.pdf</a> <a href="#fnref:41" class="footnote-back-ref">↩</a></p></li> <li id="fn:42"><p>"Power ISA Version 3.1". openpowerfoundation.org. 2020-05-01. Retrieved 2021-10-20. <a href="https://ibm.ent.box.com/s/hhjfw0x0lrbtyzmiaffnbxh2fuo0fog0" target="_blank">https://ibm.ent.box.com/s/hhjfw0x0lrbtyzmiaffnbxh2fuo0fog0</a> <a href="#fnref:42" class="footnote-back-ref">↩</a></p></li> <li id="fn:43"><p>"Power ISA Version 3.1". openpowerfoundation.org. 2020-05-01. Retrieved 2021-10-20. <a href="https://ibm.ent.box.com/s/hhjfw0x0lrbtyzmiaffnbxh2fuo0fog0" target="_blank">https://ibm.ent.box.com/s/hhjfw0x0lrbtyzmiaffnbxh2fuo0fog0</a> <a href="#fnref:43" class="footnote-back-ref">↩</a></p></li> <li id="fn:44"><p>"RISC-V ISA Specifications". Retrieved 17 June 2019. <a href="https://riscv.org/specifications/" target="_blank">https://riscv.org/specifications/</a> <a href="#fnref:44" class="footnote-back-ref">↩</a></p></li> <li id="fn:45"><p>Oracle SPARC Processor Documentation <a href="http://www.oracle.com/technetwork/server-storage/sun-sparc-enterprise/documentation/sparc-processor-2516655.html" target="_blank">http://www.oracle.com/technetwork/server-storage/sun-sparc-enterprise/documentation/sparc-processor-2516655.html</a> <a href="#fnref:45" class="footnote-back-ref">↩</a></p></li> <li id="fn:46"><p>SPARC Architecture License <a href="http://sparc.org/technical-documents/#ArchLic" target="_blank">http://sparc.org/technical-documents/#ArchLic</a> <a href="#fnref:46" class="footnote-back-ref">↩</a></p></li> </ol>