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<h2 id="features">Features</h2> <p>M.2 modules can integrate multiple functions, including the following device classes: <a href="/facts/Wi-Fi/u94quCsx">Wi-Fi</a>, <a href="/facts/Bluetooth/sWAjpMrj">Bluetooth</a>, <a href="/facts/Satellite_navigation/lVgPlF5v">satellite navigation</a>, <a href="/facts/Near_field_communication/awqd3Ea8">near field communication</a> (NFC), <a href="/facts/Digital_radio/X0Kp5l8E">digital radio</a>, <a href="/facts/WiGig/9u8SBuDs">WiGig</a>, <a href="/facts/Wireless_WAN/zT4Qcpbz">wireless WAN</a> (WWAN), and <a href="/facts/Solid-state_drive/aMHBy8gU">solid-state drives</a> (SSDs).<a class="footnote-ref" id="fnref:10" href="#fn:10"><sup>10</sup></a> The <a href="/facts/SATA_3.2/dW8yAMm8">SATA revision 3.2</a> specification, in its gold revision as of August 2013<a href="https://en.wikipedia.org/w/index.php?title=M.2&action=edit">[update]</a>, standardizes M.2 as a new format for storage devices and specifies its hardware layout.<a class="footnote-ref" id="fnref:11" href="#fn:11"><sup>11</sup></a>: 12 <a class="footnote-ref" id="fnref:12" href="#fn:12"><sup>12</sup></a> <a href="/facts/Bus_(computing)/R45TKwS7">Buses</a> exposed through the M.2 connector include <a href="/facts/PCI_Express/ADhsLCUK">PCI Express</a> (PCIe) 3.0 and newer, <a href="/facts/Serial_ATA/dW8yAMm8">Serial ATA</a> (SATA) 3.0 and <a href="/facts/USB/XcIKWLyg">USB</a> 3.0; all these standards are <a href="/facts/Backward_compatible/FbHFBu5y">backward compatible</a>. </p><p>The M.2 specification provides up to four <a href="/facts/PCI_Express_lane/ADhsLCUK">PCI Express lanes</a> and one logical <a href="/facts/SATA_3.0/dW8yAMm8">SATA 3.0</a> (6 Gbit/s) port, and exposes them through the same connector so both PCI Express and SATA storage devices may exist in the form of M.2 modules. Exposed PCI Express lanes provide a pure PCI Express connection between the host and storage device, with no additional layers of <a href="/facts/Bus_(computing)/R45TKwS7">bus</a> abstraction.<a class="footnote-ref" id="fnref:13" href="#fn:13"><sup>13</sup></a> <a href="/facts/PCI-SIG/J8RzfTsQ">PCI-SIG</a> M.2 specification, in its revision 1.0 as of December 2013<a href="https://en.wikipedia.org/w/index.php?title=M.2&action=edit">[update]</a>, provides detailed M.2 specifications.<a class="footnote-ref" id="fnref:14" href="#fn:14"><sup>14</sup></a>: 12 <a class="footnote-ref" id="fnref:15" href="#fn:15"><sup>15</sup></a> </p> <h3>Storage interfaces</h3> <p>Three options are available for the logical device interfaces and command sets used for interfacing with M.2 storage devices, which may be used depending on the type of M.2 storage device and available <a href="/facts/Operating_system/8XTuvMh2">operating system</a> support:<a class="footnote-ref" id="fnref:16" href="#fn:16"><sup>16</sup></a>: 14 <a class="footnote-ref" id="fnref:17" href="#fn:17"><sup>17</sup></a><a class="footnote-ref" id="fnref:18" href="#fn:18"><sup>18</sup></a> </p> Legacy SATA Used for SATA SSDs, and interfaced through the AHCI driver and <a href="/facts/Legacy_system/YvYjMcCz">legacy</a> SATA 3.0 (6 Gbit/s) port exposed through the M.2 connector. PCI Express using AHCI Used for PCI Express SSDs and interfaced through the <a href="/facts/AHCI/TKjwWqKq">AHCI</a> driver and provided PCI Express lanes, providing <a href="/facts/Backward_compatibility/FbHFBu5y">backward compatibility</a> with widespread SATA support in operating systems at the cost of lower performance. AHCI was developed when the purpose of a <a href="/facts/Host_bus_adapter/nQbbDHF2">host bus adapter</a> (HBA) in a system was to connect the CPU/memory subsystem with a much slower storage subsystem based on rotating <a href="/facts/Magnetic_storage/QaK6oArm">magnetic media</a>; as a result, AHCI has some inherent <a href="/facts/NVMe_vs_AHCI/Ye7N4elE">inefficiencies</a> when applied to SSD devices, which behave much more like <a href="/facts/Random-access_memory/DuD4bxh6">RAM</a> than like spinning media. PCI Express using NVMe Used for PCI Express SSDs and interfaced through the <a href="/facts/NVMe/Ye7N4elE">NVMe</a> driver and provided PCI Express lanes, as a high-performance and scalable host controller interface designed and optimized especially for interfacing with PCI Express SSDs. NVMe has been designed from the ground up, capitalizing on the low <a href="/facts/Latency_(engineering)/6Bjhn30H">latency</a> and enhanced <a href="/facts/Parallelism_(computing)/nQzcpzQt">parallelism</a> of PCI Express SSDs, and complementing the <a href="/facts/Parallelism_(computing)/nQzcpzQt">parallelism</a> of contemporary <a href="/facts/Central_processing_unit/Jxp1bqMV">CPUs</a>, platforms and applications. At a high level, primary <a href="/facts/NVMe_vs_AHCI/Ye7N4elE">advantages of NVMe over AHCI</a> relate to NVMe's ability to exploit parallelism in host hardware and software, based on its design advantages that include data transfers with fewer stages, greater depth of <a href="/facts/Command_queue/VRaIl654">command queues</a>, and more efficient <a href="/facts/Interrupt/Mm6C4rpc">interrupt</a> processing. <h2 id="form-factors-and-keying">Form factors and keying</h2> <p>The M.2 standard is based on the <a href="/facts/MSATA/dW8yAMm8">mSATA</a> standard, which uses the existing <a href="/facts/PCI_Express_Mini_Card/ADhsLCUK">PCI Express Mini Card</a> (Mini PCIe) <a href="/facts/Form_factor_(design)/pbWg5yAR">form factor</a> and connector. M.2 adds the possibility of larger <a href="/facts/Printed_circuit_board/muSR2p43">printed circuit boards</a> (PCBs), allowing longer modules and double-sided component population. Consequently, M.2 <a href="/facts/SSD/aMHBy8gU">SSD</a> modules can provide double the storage capacity within the footprint of an mSATA device.<a class="footnote-ref" id="fnref:19" href="#fn:19"><sup>19</sup></a>: 20, 22–23 <a class="footnote-ref" id="fnref:20" href="#fn:20"><sup>20</sup></a><a class="footnote-ref" id="fnref:21" href="#fn:21"><sup>21</sup></a> </p><p>M.2 modules are rectangular, with an <a href="/facts/Edge_connector/AXBbRgIV">edge connector</a> on one side and a semicircular mounting hole at the center of the opposite edge. The edge connector has 75 positions with up to 67 pins, employing a 0.5 mm <a href="/facts/Pin_pitch/fazIw78t">pitch</a> and offsetting the pins on opposing sides of the PCB from each other. Each pin on the connector is rated for up to 50 <a href="/facts/Volt/KF18MXP2">V</a> and 0.5 <a href="/facts/Ampere/MScqkCgz">A</a>, while the connector itself is specified to endure 60 mating cycles.<a class="footnote-ref" id="fnref:22" href="#fn:22"><sup>22</sup></a>: 6 However, many M.2 slots (Socket 1, 2 and 3) found on motherboards only provide up to 3.3 <a href="/facts/Volt/KF18MXP2">V</a> power.<a class="footnote-ref" id="fnref:23" href="#fn:23"><sup>23</sup></a><a class="footnote-ref" id="fnref:24" href="#fn:24"><sup>24</sup></a><a class="footnote-ref" id="fnref:25" href="#fn:25"><sup>25</sup></a> </p><p>The M.2 standard allows module widths of 12, 16, 22 and 30 mm, and lengths of 16, 26, 30, 38, 42, 60, 80 and 110 mm. Initial line-up of the commercially available M.2 expansion cards is 22 mm wide, with varying lengths of 30, 42, 60, 80 and 110 mm.<a class="footnote-ref" id="fnref:26" href="#fn:26"><sup>26</sup></a><a class="footnote-ref" id="fnref:27" href="#fn:27"><sup>27</sup></a><a class="footnote-ref" id="fnref:28" href="#fn:28"><sup>28</sup></a><a class="footnote-ref" id="fnref:29" href="#fn:29"><sup>29</sup></a> The codes for the M.2 module sizes contain both the width and length of a particular module; for example, "2242" as a module code means that the module is 22 mm wide and 42 mm long, while "2280" denotes a module 22 mm wide and 80 mm long. </p><p>An M.2 module is installed into a mating connector provided by the host's circuit board, and a single mounting screw secures the module into place. Components may be mounted on either side of the module, with the actual module type limiting how thick the components can be; the maximum allowable thickness of components is 1.5 mm per side, and the thickness of the PCB is 0.8 mm ± 10%.<a class="footnote-ref" id="fnref:30" href="#fn:30"><sup>30</sup></a> Different host-side connectors are used for single- and double-sided M.2 modules, providing different amounts of space between the M.2 expansion card and the host's PCB.<a class="footnote-ref" id="fnref:31" href="#fn:31"><sup>31</sup></a><a class="footnote-ref" id="fnref:32" href="#fn:32"><sup>32</sup></a><a class="footnote-ref" id="fnref:33" href="#fn:33"><sup>33</sup></a> Circuit boards on the hosts are usually designed to accept multiple lengths of M.2 modules, which means that the sockets capable of accepting longer M.2 modules usually also accept shorter ones by providing different positions for the mounting screw.<a class="footnote-ref" id="fnref:34" href="#fn:34"><sup>34</sup></a><a class="footnote-ref" id="fnref:35" href="#fn:35"><sup>35</sup></a> </p> M.2 module keying and provided interfaces<a class="footnote-ref" id="fnref:36" href="#fn:36"><sup>36</sup></a>: 8 <a class="footnote-ref" id="fnref:37" href="#fn:37"><sup>37</sup></a>: 3 <a class="footnote-ref" id="fnref:38" href="#fn:38"><sup>38</sup></a><a class="footnote-ref" id="fnref:39" href="#fn:39"><sup>39</sup></a><a class="footnote-ref" id="fnref:40" href="#fn:40"><sup>40</sup></a><table><tbody><tr><th>KeyID</th><th>Notchedpins</th><th>Provided interfaces</th><th>Dimensions</th><th>Uses</th></tr><tr><td>A (Socket 1)</td><td>8–15</td><td>2 times <a href="/facts/PCIe/ADhsLCUK">PCIe</a> ×1, USB 2.0, <a href="/facts/I2C/dKBBhs4U">I2C</a> and <a href="/facts/DisplayPort/rJSvGhBN">DP</a> ×4</td><td>1630, 2230, 3030</td><td><a href="/facts/Wi-Fi/u94quCsx">Wi-Fi</a>, <a href="/facts/WWAN/zT4Qcpbz">WWAN</a>, <a href="/facts/GPS_receiver/MmeJ3XWK">GPS</a>, <a href="/facts/Bluetooth/sWAjpMrj">Bluetooth</a>, <a href="/facts/Near-field_communication/awqd3Ea8">NFC</a></td></tr><tr><td>B (Socket 2)</td><td>12–19</td><td><a href="/facts/SATA/dW8yAMm8">SATA</a>, PCIe ×2, USB 2.0 and 3.0, audio, <a href="/facts/User_identity_module/NUeSqoG1">UIM</a>, <a href="/facts/HSIC/dYtCS1pj">HSIC</a>, <a href="/facts/SSIC/dYtCS1pj">SSIC</a>, I2C and <a href="/facts/SMBus/tKmAhz5l">SMBus</a></td><td>2230, 2242, 2260, 2280, 22110</td><td><a href="/facts/SSD/aMHBy8gU">SSD</a></td></tr><tr><td>C</td><td>16–23</td><td rowspan="2" colspan="3">Reserved for future use</td></tr><tr><td>D</td><td>20–27</td></tr><tr><td>E (Socket 1)</td><td>24–31</td><td>2 times PCIe ×1, USB 2.0, <a href="/facts/I2C/dKBBhs4U">I2C</a>, <a href="/facts/Secure_Digital_Input_Output/RLL9UTly">SDIO</a>, <a href="/facts/UART/xMntJcsI">UART</a>, <a href="/facts/PCM/5gdfjtH3">PCM</a> and <a href="/facts/CNVi/xnqcMEJ3">CNVi</a></td><td>1630, 2230, 3030</td><td><a href="/facts/Wi-Fi/u94quCsx">Wi-Fi</a>, <a href="/facts/WWAN/zT4Qcpbz">WWAN</a>, <a href="/facts/GPS_receiver/MmeJ3XWK">GPS</a>, <a href="/facts/Bluetooth/sWAjpMrj">Bluetooth</a>, <a href="/facts/Near-field_communication/awqd3Ea8">NFC</a></td></tr><tr><td>A+E (Socket 1)</td><td>8–15 and 24–31</td><td>2 times PCIe ×1, USB 2.0 and <a href="/facts/CNVi/xnqcMEJ3">CNVi</a></td><td>1630, 2230, 3030</td><td><a href="/facts/Wi-Fi/u94quCsx">Wi-Fi</a>, <a href="/facts/WWAN/zT4Qcpbz">WWAN</a>, <a href="/facts/GPS_receiver/MmeJ3XWK">GPS</a>, <a href="/facts/Bluetooth/sWAjpMrj">Bluetooth</a>, <a href="/facts/Near-field_communication/awqd3Ea8">NFC</a></td></tr><tr><td>F</td><td>28–35</td><td colspan="3">Future Memory Interface (FMI)</td></tr><tr><td>G</td><td>39–46</td><td colspan="3">Reserved for custom use (unused in the M.2 specification)</td></tr><tr><td>H</td><td>43–50</td><td rowspan="4" colspan="3">Reserved for future use</td></tr><tr><td>J</td><td>47–54</td></tr><tr><td>K</td><td>51–58</td></tr><tr><td>L</td><td>55–62</td></tr><tr><td>M (Socket 3)</td><td>59–66</td><td>SATA, PCIe ×4, and SMBus</td><td>2230, 2242, 2260, 2280, 22110</td><td><a href="/facts/SSD/aMHBy8gU">SSD</a></td></tr><tr><td>B+M (Socket 2)</td><td>12-19 and 59–66</td><td>SATA, PCIe ×2, and SMBus</td><td>2230, 2242, 2260, 2280, 22110</td><td><a href="/facts/SSD/aMHBy8gU">SSD</a></td></tr></tbody></table> Maximum component thickness on M.2 modules<a class="footnote-ref" id="fnref:41" href="#fn:41"><sup>41</sup></a>: 8 <a class="footnote-ref" id="fnref:42" href="#fn:42"><sup>42</sup></a>: 3 <table><tbody><tr><th>TypeID</th><th>Top side</th><th>Bottom side</th></tr><tr><td>S1</td><td>1.20 mm</td><td>—</td></tr><tr><td>S2</td><td>1.35 mm</td><td>—</td></tr><tr><td>S3</td><td>1.50 mm</td><td>—</td></tr><tr><td>D1</td><td>1.20 mm</td><td>1.35 mm</td></tr><tr><td>D2</td><td>1.35 mm</td><td>1.35 mm</td></tr><tr><td>D3</td><td>1.50 mm</td><td>1.35 mm</td></tr><tr><td>D4</td><td>1.50 mm</td><td>0.70 mm</td></tr><tr><td>D5</td><td>1.50 mm</td><td>1.50 mm</td></tr></tbody></table> <p>The PCB of an M.2 module provides a 75-position edge connector; depending on the type of module, certain pin positions are removed to present one or more keying notches. Host-side M.2 connectors (sockets) may populate one or more mating key positions, determining the type of modules accepted by the host; as of April 2014<a href="https://en.wikipedia.org/w/index.php?title=M.2&action=edit">[update]</a>, host-side connectors are available with only one mating key position populated (either B or M).<a class="footnote-ref" id="fnref:43" href="#fn:43"><sup>43</sup></a><a class="footnote-ref" id="fnref:44" href="#fn:44"><sup>44</sup></a><a class="footnote-ref" id="fnref:45" href="#fn:45"><sup>45</sup></a> Furthermore, M.2 sockets keyed for SATA or two PCI Express lanes (PCIe ×2) are referred to as "socket 2 configuration" or "socket 2", while the sockets keyed for four PCI Express lanes (PCIe ×4) are referred to as "socket 3 configuration" or "socket 3".<a class="footnote-ref" id="fnref:46" href="#fn:46"><sup>46</sup></a>: 15 <a class="footnote-ref" id="fnref:47" href="#fn:47"><sup>47</sup></a> </p><p>For example, M.2 modules with two notches in B and M positions use up to two PCI Express lanes and provide broader compatibility at the same time, while the M.2 modules with only one notch in the M position use up to four PCI Express lanes; both examples may also provide SATA storage devices. Similar keying applies to M.2 modules that utilize provided USB 3.0 connectivity.<a class="footnote-ref" id="fnref:48" href="#fn:48"><sup>48</sup></a><a class="footnote-ref" id="fnref:49" href="#fn:49"><sup>49</sup></a><a class="footnote-ref" id="fnref:50" href="#fn:50"><sup>50</sup></a> </p><p>Various types of M.2 modules are denoted using the "WWLL-HH-K-K" or "WWLL-HH-K" naming schemes, in which "WW" and "LL" specify the module width and length in millimeters, respectively. The "HH" part specifies, in an encoded form, whether a module is single- or double-sided, and the maximum allowed thickness of mounted components; possible values are listed in the right table above. Module keying is specified by the "K-K" part, in an encoded form using the key IDs from the left table above; it can also be specified as "K" only, if a module has only one keying notch.<a class="footnote-ref" id="fnref:51" href="#fn:51"><sup>51</sup></a><a class="footnote-ref" id="fnref:52" href="#fn:52"><sup>52</sup></a> </p><p>Beside socketed modules, the M.2 standard also includes the option for having permanently <a href="/facts/Soldering/fod6dLHD">soldered</a> single-sided modules.<a class="footnote-ref" id="fnref:53" href="#fn:53"><sup>53</sup></a> </p> <h2 id="alternative-standards">Alternative standards</h2> <h3>NGSFF</h3> <p>In 2017, Samsung introduced a new form factor called <i>Next Generation Small Form Factor</i> (NGSFF), also known as NF1 or M.3, which may replace <a href="/facts/U.2/tm6F04h0">U.2</a> in server applications.<a class="footnote-ref" id="fnref:54" href="#fn:54"><sup>54</sup></a> The NGSFF connector is electrically and dimensionally compatible with M.2 (revision 1.1)'s connector; new functionality is achieved through previously unused (N/C) pins.<a class="footnote-ref" id="fnref:55" href="#fn:55"><sup>55</sup></a> The main changes compared to M.2 are: </p> <ul><li>The width (or "height") of the SSD is increased from 22 mm to 30.5 mm; the thickness is increased from 3.88 mm to 4.38 mm. These changes allow more NAND chips to be fitted onto an SSD while still fitting inside a <a href="/facts/Rack_unit/Fh9hl0cc">rack unit</a>.<a class="footnote-ref" id="fnref:56" href="#fn:56"><sup>56</sup></a></li> <li>New pins for 12 V power. Devices are supposed to mainly use 12 V power instead of the old 3.3 V, which has been made optional.<a class="footnote-ref" id="fnref:57" href="#fn:57"><sup>57</sup></a></li> <li>Ability to run two PCIe ports (each with two lanes) on one NGSFF port.<a class="footnote-ref" id="fnref:58" href="#fn:58"><sup>58</sup></a></li> <li>Features for rackmount servers: hotswap support, indicator LEDs, SSD tray (with new screw holes).<a class="footnote-ref" id="fnref:59" href="#fn:59"><sup>59</sup></a></li></ul> <p>In 2018, the PCI-SIG issued a warning that NGSFF's new pin usage clashes with the pin usage in the upcoming 1.2 revision of the M.2 standard. The new revision uses some of the previously non-connected (N/C) pins to deliver 1.8 V power and USB 2.0 data on the "M" socket. Samsung has sought to standardize its NGSFF/NF1 through <a href="/facts/JEDEC/EM7UoQlJ">JEDEC</a>, but the process appears to have stalled.<a class="footnote-ref" id="fnref:60" href="#fn:60"><sup>60</sup></a> </p> <h3>XFM</h3> <p>JEDEC JESD233 is another specification called <i>Crossover Flash Memory</i> (XFM) for XFM Embedded and Removable Memory Devices (XFMD). It targets to replace the M.2 form factor with a significantly smaller one (also called XT2), so that it can also be designed as an alternative to soldered memory. XFM Express utilizes a <a href="/facts/NVM_Express/Ye7N4elE">NVMe</a> logical interface over a <a href="/facts/PCI_Express/ADhsLCUK">PCI Express</a> physical interface.<a class="footnote-ref" id="fnref:61" href="#fn:61"><sup>61</sup></a><a class="footnote-ref" id="fnref:62" href="#fn:62"><sup>62</sup></a> </p> <h2 id="gallery">Gallery</h2> <h2 id="see-also">See also</h2> <ul> <li>Electronics portal</li></ul> <ul><li><a href="/facts/Enterprise_and_Data_Center_Standard_Form_Factor/VS6DU2z8">Enterprise and Data Center Standard Form Factor</a> (EDSFF)</li> <li><a href="/facts/List_of_interface_bit_rates/RJzvfP0g">List of interface bit rates</a></li> <li><a href="/facts/NVM_Express/Ye7N4elE">NVM Express</a> (NVMe)</li> <li><a href="/facts/Solid-state_drive/aMHBy8gU">Solid-state drive § Configurations</a></li> <li><a href="/facts/U.2/tm6F04h0">U.2</a></li></ul> <h2 id="external-links">External links</h2> Wikimedia Commons has media related to M.2. <ul><li><a href="https://www.sata-io.org">Serial ATA International Organization</a> (SATA-IO) official website</li> <li><a href="https://www.pcisig.com">Peripheral Component Interconnect Special Interest Group</a> (PCI-SIG) official website</li> <li><a href="https://arstechnica.com/gadgets/2015/02/understanding-m-2-the-interface-that-will-speed-up-your-next-ssd">Understanding M.2, the interface that will speed up your next SSD</a>, <i><a href="/facts/Ars_Technica/zvnX7pnh">Ars Technica</a></i>, February 9, 2015, by Andrew Cunningham</li> <li><a href="https://lwn.net/Articles/547903">LFCS: Preparing Linux for nonvolatile memory devices</a>, <a href="/facts/LWN.net/8uTsltvM">LWN.net</a>, April 19, 2013, by Jonathan Corbet</li> <li><a href="https://web.archive.org/web/20140202110152/http://www.snia.org/sites/default/files/SNIASSSIPCIe101WhitePaper1.12013.pdf">PCIe SSD 101: An Overview of Standards, Markets and Performance</a>, <a href="/facts/Storage_Networking_Industry_Association/nWXbIQI2">SNIA</a>, August 2013, archived from the original on February 2, 2014</li> <li><a href="https://www.congatec.com/fileadmin/user_upload/Documents/Application_Notes/AN43_M.2_Pinout_Descriptions_and_Reference_Designs.pdf">M.2 Pinout Descriptions and Reference Designs</a>, January 28, 2020, an application note from Congatec</li> <li><a href="https://patents.google.com/patent/US20130294023">Interface card mount</a> – US patent 20130294023, November 7, 2013, assigned to Raphael Gay</li></ul> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>Gillis, Alexander S. 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