Menu
Home
People
Places
Arts
History
Plants & Animals
Science
Life & Culture
Technology
Reference.org
CoreConnect
open-in-new
<h2 id="processor-local-bus-plb">Processor Local Bus (PLB)</h2> <ul><li>General processor local bus</li> <li>Synchronous, nonmultiplexed bus</li> <li>Separate Read, Write data buses</li> <li>Supports concurrent Read, Writes</li> <li>Multimaster, programmable-priority, arbitrated bus</li> <li>32-bit up to 64-bit address</li> <li>32-/64-/128-bit implementations (to 256-bit)</li> <li>66/133/183 MHz (32-/64-/128-bit)</li> <li>Pipelined, supports early split transactions</li> <li>Overlapped arbitration (last cycle)</li> <li>Supports fixed, variable-length bursts</li> <li>Bus locking</li> <li>High bandwidth capabilities, up to 2.9 <a href="/facts/Gigabyte/s2hb2SEg">GB</a>/s.</li></ul> <h2 id="on-chip-peripheral-bus-opb">On-chip Peripheral Bus (OPB)</h2> <ul><li>Peripheral bus for slower devices</li> <li>Synchronous, nonmultiplexed bus</li> <li>Multimaster, arbitrated bus</li> <li>Up to a 64-bit address bus</li> <li>Separate 32-bit Read, Write buses</li> <li>Pipelined transactions</li> <li>Overlapped arbitration (last cycle)</li> <li>Supports bursts</li> <li>Dynamic bus sizing, 8-, 16-, 32-bit devices</li> <li>Single-cycle data transfers</li> <li>Bus locking (parking)</li></ul> <h2 id="device-control-register-dcr-bus">Device Control Register (DCR) bus</h2> <p>This bus: </p> <ul><li>provides fully <a href="/facts/Synchronization_(computer_science)/n7ID76uM">synchronous</a> movement of <a href="/facts/Processor_register/32RvbUdz">GPR</a> data between <a href="/facts/Central_processing_unit/Jxp1bqMV">CPU</a> and slave logic</li> <li>functions as a synchronous, nonmultiplexed bus</li> <li>has separate buses to read and to write data</li> <li>consists of a single-master, multiple-slave bus</li> <li>includes a 10-bit address bus</li> <li>features 32-bit data buses</li> <li>uses two-cycle minimum Read/Write cycles</li> <li>utilizes distributed multiplexer architecture</li> <li>supports 8-, 16-, and 32-bit devices</li> <li>performs single-cycle data transfers</li></ul> <h2 id="external-links">External links</h2> <ul><li><a href="https://web.archive.org/web/20090129183058/http://www-01.ibm.com/chips/techlib/techlib.nsf/products/CoreConnect_Bus_Architecture">CoreConnect bus architecture, IBM.com</a></li> <li><a href="https://web.archive.org/web/20040616075914/http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=dr_pcentral_coreconnect">CoreConnect Technology , Xilinx.com</a></li> <li><a href="https://web.archive.org/web/20071021093848/http://www-03.ibm.com/technology/ges/semiconductor/power/licensing/coreconnect/crcon_ugl.html">CoreConnect licensing, IBM.com</a></li> <li><a href="https://web.archive.org/web/20160303185318/http://electronicdesign.com/Articles/Index.cfm?AD=1&ArticleID=4089">CoreConnect: The On-Chip Bus System, ElectronicDesign.com</a></li> <li><a href="https://web.archive.org/web/20110520034719/https://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/2F9323ECBC8CFEE0872570F4005C5739/%24file/DcrBus.pdf">Device Control Register Bus 3.5 Architecture Specifications</a></li></ul>