ggNMOS

<h2 id="structure">Structure</h2>
<p>As the name implies, a ggNMOS device consists of a relatively wide NMOS device in which the gate, source, and body are tied together to ground.  The drain of the ggNMOS is connected to the I/O pad under protection.  A <a href="/facts/Parasitic_structure/h7EmtL9D">parasitic</a> NPN <a href="/facts/Bipolar_junction_transistor/9BMcGv5Q">bipolar junction transistor</a> (BJT) is thus formed with the drain (<a href="/facts/N-type_semiconductor/d9GPL5tV">n-type</a>) acting as the collector, the base/source combination (n-type) as the emitter, and the <a href="/facts/Wafer_(electronics)/lCBJAoUL">substrate</a> (<a href="/facts/P-type_semiconductor/d9GPL5tV">p-type</a>) as the base.  As is explained below, a key element to the operation of the ggNMOS is the <a href="/facts/Parasitic_resistance/aJf6UtNm">parasitic resistance</a> present between the emitter and base terminals of the parasitic npn BJT.  This resistance is a result of the finite <a href="/facts/Electrical_conductivity/akyCKvMy">conductivity</a> of the p-type doped substrate.
</p>

<h2 id="operation">Operation</h2>
<p>When a positive ESD event appears upon the I/O pad (drain), the collector-base junction of the parasitic NPN BJT becomes reverse biased to the point of <a href="/facts/Avalanche_breakdown/PD2E9dPy">avalanche breakdown</a>.  At this point, the positive current flowing from the base to ground induces a voltage potential across the parasitic resistor, causing a positive voltage to appear across the base-emitter junction.  The positive VBE forward biases this junction, triggering the parasitic NPN BJT.<a class="footnote-ref" id="fnref:3" href="#fn:3"><sup>3</sup></a>
</p>

<p><a href="https://www.researchgate.net/publication/4133911_Modeling_MOS_snapback_for_circuit-level_ESD_simulation_using_BSIM3_and_VBIC_models">https://www.researchgate.net/publication/4133911_Modeling_MOS_snapback_for_circuit-level_ESD_simulation_using_BSIM3_and_VBIC_models</a>
</p>

<h2 id="references">References</h2>

<ol>
<li id="fn:1"><p>Issaq, E.; Merri, R. (1993). ESD design methodology. Electrical Overstress/Electrostatic Discharge Symposium. Lake Buena Vista, Florida. pp. 223–237. <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li>
<li id="fn:2"><p>Green, T. (1988). A review of EOS/ESD field failures in military equipment. Electrical Overstress/Electrostatic Discharge Symposium. Anaheim, California. pp. 7–14. <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li>
<li id="fn:3"><p>Wang, Albert (2002). On-Chip ESD Protection for Integrated Circuits: An IC Design Perspective. Norwell, MA, USA: Kluwer Academic Publishing. ISBN 0792376471. <a href="0792376471" target="_blank">0792376471</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li>
</ol>

ggNMOS open-in-new

ggNMOS