Open Core Protocol

<h2 id="advantages">Advantages</h2>
<ul><li>Eliminates the ongoing task of interface protocol (re)definition, verification, documentation and support</li>
<li>Readily adapts to support new core capabilities</li>
<li>Test bench portability simplifies (re)verification</li>
<li>Limits test suite modifications for core enhancements</li>
<li>Interfaces to any bus structure or on-chip network</li>
<li>Delivers industry-standard flexibility and reuse</li>
<li>Point-to-point protocol can directly interface two cores</li></ul>
<h2 id="disadvantages">Disadvantages</h2>
<ul><li>Neither <a href="/facts/Altera/66c0Gh0R">Altera</a> nor <a href="/facts/Xilinx/rbXfxqqG">Xilinx</a>, the two largest <a href="/facts/Field-programmable_gate_array/M8LSGcAU">FPGA</a> vendors, supports this protocol.</li></ul>

<h2 id="external-links">External links</h2>
<ul><li><a href="https://accellera.org/downloads/standards/ocp/">Official website</a> </li></ul>

<h2 id="references">References</h2>

<ol>
<li id="fn:1"><p>William G. Wong.
"Understanding FPGA Processor Interconnects".
2012. <a href="https://www.electronicdesign.com/technologies/fpgas/article/21795951/understanding-fpga-processor-interconnects" target="_blank">https://www.electronicdesign.com/technologies/fpgas/article/21795951/understanding-fpga-processor-interconnects</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li>
<li id="fn:2"><p>"Altera, others join open core protocol group". <a href="https://www.eetimes.com/altera-others-join-open-core-protocol-group/" target="_blank">https://www.eetimes.com/altera-others-join-open-core-protocol-group/</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li>
</ol>

Open Core Protocol open-in-new

Open Core Protocol