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<h2 id="categories">Categories</h2> <ul><li><i>Base</i> – Most of Book I and Book II</li> <li><i>Server</i> – Book III-S</li> <li><i>Embedded</i> – Book III-E</li> <li><i>Misc</i> – floating point, vector, signal processing, cache locking, decimal floating point, etc.</li></ul> <h2 id="books">Books</h2> <p>The Power ISA specification is divided into five parts, called "books": </p> <ul><li><i>Book I</i> – <i>User Instruction Set Architecture</i> covers the base instruction set available to the application programmer. Memory reference, flow control, Integer, floating point, numeric acceleration, application-level programming. It includes chapters regarding auxiliary processing units like <a href="/facts/Digital_signal_processor/YuBXweos">digital signal processors</a> (DSPs) and the <a href="/facts/AltiVec/Vn1DY71U">AltiVec</a> extension.</li> <li><i>Book II</i> – <i>Virtual Environment Architecture</i> defines the storage model available to the application programmer, including timing, synchronization, cache management, storage features, byte ordering.</li> <li><i>Book III</i> – <i>Operating Environment Architecture</i> includes exceptions, interrupts, memory management, debug facilities and special control functions. It is divided into two parts. <ul><li><i>Book III-S</i> – Defines the supervisor instructions used for general-purpose/server implementations. It is mainly the contents of the Book III of the former PowerPC ISA.</li> <li><i>Book III-E</i> – Defines the supervisor instructions used for embedded applications. It is derived from the former PowerPC Book E.</li></ul></li> <li><i>Book VLE</i> – <i>Variable Length Encoded Instruction Architecture</i> defines alternative instructions and definitions from Books I–III, intended for higher instruction density and very-low-end applications. They use 16-bit instructions and big-endian byte ordering.</li></ul> <h3>Compliancy</h3> <p>New in version 3 of the Power ISA is that you don't have to implement the entire specification to be compliant. The sprawl of instructions and technologies has made the complete specification unwieldy, so the OpenPOWER Foundation have decided to enable tiered compliancy. </p><p>These levels include optional and mandatory requirements, however one common misunderstanding is that there is nothing stopping an implementation from being compliant at a lower level but having additional selected functions from higher levels and custom extensions. It is however recommended that an option be provided to disable any added functions beyond the design's declared subset level. </p><p>A design must be compliant at its declared subset level to make use of the Foundation's protection regarding use of <a href="/facts/Intellectual_property/PqHW9mVP">intellectual property</a>, be it <a href="/facts/Patent/LjT2bG3A">patents</a> or <a href="/facts/Trademark/B23H8IS0">trademarks</a>. This is explained in the OpenPOWER EULA.<a class="footnote-ref" id="fnref:1" href="#fn:1"><sup>1</sup></a> </p><p>A compliant design must:<a class="footnote-ref" id="fnref:2" href="#fn:2"><sup>2</sup></a> </p> <ul><li>Support the <i>Base</i> architecture</li> <li>And support at least one of the subsets <ul><li><i>SFS</i> – Scalar Fixed-point Subset. 129 instructions. Basic fixed point and load/store instructions, which is really the <i>Base</i> architecture.</li> <li><i>SFFS</i> – Scalar Fixed-point + Floating-point Subset. 214 instructions. Adding floating-point operations to the Base.</li> <li><i>LCS</i> – Linux Compliancy Subset. 962 instructions. Intended for server grade Linux, adding features like 64-bit, optional SIMD/VSX, Radix MMU, little-endian mode and hypervisor support.</li> <li><i>ACS</i> – <a href="/facts/IBM_AIX/cRWERua2">AIX</a> Compliancy Subset. 1099 instructions. Intended to run AIX, adding features like decimal and quad-precision floating point, big-endian mode and symmetric multiprocessing.</li></ul></li> <li>May include any of the features of the LCS and ACS as Optional or pick from the Always Optional features like matrix math and power management.</li> <li>Optional features, if chosen, must be implemented in their entirety (partial implementation of an Optional feature is not permitted)</li> <li>May include Custom extensions, specific to the implementation, implemented in the <i>Architecture Sandbox</i>.</li></ul> <p>If the extension is general-purpose enough, the OpenPOWER Foundation asks that implementors submit it as a Request for Comments (RFC) to the <a href="https://openpower.foundation/groups/isa/">OpenPOWER ISA Workgroup</a>. Note that it is not strictly necessary to join the OpenPOWER Foundation to submit RFCs.<a class="footnote-ref" id="fnref:3" href="#fn:3"><sup>3</sup></a> </p> <ul><li>Much may be implemented in either hardware or firmware.</li></ul> <h4>EABI and Linux Compliancy discrepancy</h4> <p>The EABI specifications predate the announcement and creation of the Compliancy subsets. </p><p>Regarding the Linux Compliancy subset having VSX (SIMD) optional: in 2003–4, 64-bit EABI v1.9 made SIMD optional,<a class="footnote-ref" id="fnref:4" href="#fn:4"><sup>4</sup></a> but in July 2015, to improve performance for IBM POWER9 systems, SIMD was made mandatory in EABI v2.0.<a class="footnote-ref" id="fnref:5" href="#fn:5"><sup>5</sup></a> This discrepancy between SIMD being optional in the Linux Compliancy level but mandatory in EABI v2.0 cannot be rectified without considerable effort: backwards incompatibility for <a href="/facts/Linux_distribution/0vVl4N4f">Linux distributions</a> is not a viable option. At present this leaves new OpenPOWER implementors wishing to run standard Linux distributions having to implement a massive 962 instructions. By contrast, RISC-V RV64GC, the minimum to run Linux, requires only 165.<a class="footnote-ref" id="fnref:6" href="#fn:6"><sup>6</sup></a> </p> <h2 id="specifications">Specifications</h2> <h3>Power ISA v.2.03</h3> <p>The specification for Power ISA v.2.03<a class="footnote-ref" id="fnref:7" href="#fn:7"><sup>7</sup></a> is based on the former PowerPC ISA v.2.02<a class="footnote-ref" id="fnref:8" href="#fn:8"><sup>8</sup></a> in <a href="/facts/POWER5/bvj1ELch">POWER5</a>+ and the Book E<a class="footnote-ref" id="fnref:9" href="#fn:9"><sup>9</sup></a> extension of the <a href="/facts/PowerPC/DqmM9y50">PowerPC</a> specification. The Book I included five new chapters regarding auxiliary processing units like <a href="/facts/Digital_signal_processor/YuBXweos">DSPs</a> and the <a href="/facts/AltiVec/Vn1DY71U">AltiVec</a> extension. </p> Compliant cores <ul><li>Freescale PowerPC <a href="/facts/PowerPC_e200/y0WGqFPJ">e200</a>, <a href="/facts/PowerPC_e500/Ulh8BNca">e500</a></li> <li>IBM PowerPC <a href="/facts/PowerPC_400/X6zS1Rgu">405</a>, <a href="/facts/PowerPC_400/X6zS1Rgu">440</a>, <a href="/facts/PowerPC_400/X6zS1Rgu">460</a>, <a href="/facts/PowerPC_970/nRyX1JxX">970</a>, <a href="/facts/POWER5/bvj1ELch">POWER5</a> and <a href="/facts/POWER6/GqfSuMVM">POWER6</a></li></ul> <h3>Power ISA v.2.04</h3> <p>The specification for Power ISA v.2.04<a class="footnote-ref" id="fnref:10" href="#fn:10"><sup>10</sup></a> was finalized in June 2007. It is based on Power ISA v.2.03 and includes changes primarily to the <i>Book III-S</i> part regarding <a href="/facts/Hardware-assisted_virtualization/n4kjJLqA">virtualization</a>, <a href="/facts/Hypervisor/3gX9fKlH">hypervisor</a> functions, <a href="/facts/LPAR/4JYGqyen">logical partitioning</a> and <a href="/facts/Virtual_page/CNGruG1H">virtual page</a> handling. </p> Compliant cores <ul><li>All cores that comply with prior versions of the Power ISA</li> <li>The <a href="/facts/PWRficient/cEMqJINj">PA6T</a> core from P.A. Semi</li> <li><a href="/facts/Titan_(microprocessor)/HW41Q3xe">Titan</a> from AMCC</li></ul> <h3>Power ISA v.2.05</h3> <p>The specification for Power ISA v.2.05<a class="footnote-ref" id="fnref:11" href="#fn:11"><sup>11</sup></a> was released in December 2007. It is based on Power ISA v.2.04 and includes changes primarily to <i>Book I</i> and <i>Book III-S</i>, including significant enhancements such as decimal arithmetic (Category: Decimal Floating-Point in <i>Book I</i>) and server hypervisor improvements. </p> Compliant cores <ul><li>All cores that comply with prior versions of the Power ISA</li> <li><a href="/facts/POWER6/GqfSuMVM">POWER6</a></li> <li><a href="/facts/PowerPC_400/X6zS1Rgu">PowerPC 476</a></li></ul> <h3>Power ISA v.2.06</h3> <p>The specification for Power ISA v.2.06<a class="footnote-ref" id="fnref:12" href="#fn:12"><sup>12</sup></a> was released in February 2009, and revised in July 2010.<a class="footnote-ref" id="fnref:13" href="#fn:13"><sup>13</sup></a> It is based on Power ISA v.2.05 and includes extensions for the POWER7 processor and <a href="/facts/PowerPC_e500/Ulh8BNca">e500-mc core</a>. One significant new feature is vector-scalar floating-point instructions (<a href="/facts/AltiVec/Vn1DY71U">VSX</a>).<a class="footnote-ref" id="fnref:14" href="#fn:14"><sup>14</sup></a> <i>Book III-E</i> also includes significant enhancement for the embedded specification regarding hypervisor and virtualisation on single and multi core implementations. </p><p>The spec was revised in November 2010 to the Power ISA v.2.06 revision B spec, enhancing virtualization features.<a class="footnote-ref" id="fnref:15" href="#fn:15"><sup>15</sup></a><a class="footnote-ref" id="fnref:16" href="#fn:16"><sup>16</sup></a> </p> Compliant cores <ul><li>All cores that comply with prior versions of the Power ISA</li> <li><a href="/facts/POWER7/GKnhcYKC">POWER7</a></li> <li><a href="/facts/IBM_A2/o4VHVJE8">A2I</a></li> <li><a href="/facts/PowerPC_e500/Ulh8BNca">e500-mc</a></li> <li><a href="/facts/PowerPC_e5500/wfPUH5a2">e5500</a></li> <li><a href="/facts/PowerPC_e6500/ME0NCXEd">e6500</a></li></ul> <h3>Power ISA v.2.07</h3> <p>The specification for Power ISA v.2.07<a class="footnote-ref" id="fnref:17" href="#fn:17"><sup>17</sup></a> was released in May 2013. It is based on Power ISA v.2.06 and includes major enhancements to <a href="/facts/Logical_partition_(virtual_computing_platform)/4JYGqyen">logical partition functions</a>, <a href="/facts/Transactional_memory/N7CcDl7w">transactional memory</a>, expanded performance monitoring, new storage control features, additions to the VMX and VSX vector facilities (VSX-2), along with <a href="/facts/Advanced_Encryption_Standard/HdXGBY2Q">AES</a><a class="footnote-ref" id="fnref:18" href="#fn:18"><sup>18</sup></a>: 257 <a class="footnote-ref" id="fnref:19" href="#fn:19"><sup>19</sup></a> and <a href="/facts/Galois_Counter_Mode/bx43MwfC">Galois Counter Mode</a> (GCM), SHA-224, SHA-256,<a class="footnote-ref" id="fnref:20" href="#fn:20"><sup>20</sup></a>: 258 SHA-384 and SHA-512<a class="footnote-ref" id="fnref:21" href="#fn:21"><sup>21</sup></a>: 258 (<a href="/facts/SHA-2/P59oPeGq">SHA-2</a>) cryptographic extensions and <a href="/facts/Cyclic_redundancy_check/u2exo4sv">cyclic redundancy check</a> (CRC) <a href="/facts/Algorithm/fnl5NmRt">algorithms</a>.<a class="footnote-ref" id="fnref:22" href="#fn:22"><sup>22</sup></a> </p><p>The spec was revised in April 2015 to the Power ISA v.2.07 B spec.<a class="footnote-ref" id="fnref:23" href="#fn:23"><sup>23</sup></a><a class="footnote-ref" id="fnref:24" href="#fn:24"><sup>24</sup></a> </p> Compliant cores <ul><li>All cores that comply with prior versions of the Power ISA</li> <li><a href="/facts/POWER8/kokdP5VT">POWER8</a></li> <li><a href="/facts/IBM_A2/o4VHVJE8">A2O</a></li></ul> <h3>Power ISA v.3.0</h3> <p>The specification for Power ISA v.3.0<a class="footnote-ref" id="fnref:25" href="#fn:25"><sup>25</sup></a><a class="footnote-ref" id="fnref:26" href="#fn:26"><sup>26</sup></a> was released in November 2015. It is the first to come out after the founding of the OpenPOWER Foundation and includes enhancements for a broad spectrum of workloads and removes the server and embedded categories while retaining backwards compatibility and adds support for VSX-3 instructions. New functions include 128-bit quad-precision floating-point operations, a <a href="/facts/Random_number_generator/RtXEfbzd">random number generator</a>, hardware-assisted <a href="/facts/Garbage_collection_(computer_science)/j2vlIu7g">garbage collection</a> and hardware-enforced trusted computing. </p><p>The spec was revised in March 2017 to the Power ISA v.3.0 B spec,<a class="footnote-ref" id="fnref:27" href="#fn:27"><sup>27</sup></a><a class="footnote-ref" id="fnref:28" href="#fn:28"><sup>28</sup></a> and revised again to v3.0C in May 2020.<a class="footnote-ref" id="fnref:29" href="#fn:29"><sup>29</sup></a><a class="footnote-ref" id="fnref:30" href="#fn:30"><sup>30</sup></a><a class="footnote-ref" id="fnref:31" href="#fn:31"><sup>31</sup></a> One major change from v3.0 to v3.0B is the removal of support for hardware assisted garbage collection. The key difference between v3.0B and v3.0C is that the Compliancy Levels listed in v3.1 were also added to v3.0C. </p> Compliant cores <ul><li>All cores that comply with prior versions of the Power ISA</li> <li><a href="/facts/POWER9/1xMKJHsX">POWER9</a><a class="footnote-ref" id="fnref:32" href="#fn:32"><sup>32</sup></a></li> <li><a href="/facts/OpenPOWER_Microwatt/TCbopn4u">OpenPOWER Microwatt</a></li> <li><a href="/facts/Libre-SOC/uKm3wH7Y">Libre-SOC</a> is aiming for Embedded FP compliancy with Power ISA 3.0 only</li></ul> <h3>Power ISA v.3.1</h3> <p>The specification for Power ISA v.3.1<a class="footnote-ref" id="fnref:33" href="#fn:33"><sup>33</sup></a><a class="footnote-ref" id="fnref:34" href="#fn:34"><sup>34</sup></a> was released in May 2020. Mainly giving support for new functions introduced in Power10, but also includes the notion of optionality to the PowerISA specification. Instructions can now be eight <a href="/facts/Byte/BNHUp9Qq">bytes</a> long, "prefixed instructions", compared to the usual four byte "word instructions". A lot of new functions to SIMD and VSX instructions are also added. VSX and the SVP64 extension provide hardware support for 16-bit half precision floats.<a class="footnote-ref" id="fnref:35" href="#fn:35"><sup>35</sup></a><a class="footnote-ref" id="fnref:36" href="#fn:36"><sup>36</sup></a> </p><p>One key benefit of the new 64-bit prefixed instructions is the extension of immediates in branches to 34-bit. </p><p>The spec was revised in September 2021 to the Power ISA v.3.1B spec.<a class="footnote-ref" id="fnref:37" href="#fn:37"><sup>37</sup></a><a class="footnote-ref" id="fnref:38" href="#fn:38"><sup>38</sup></a> </p><p>The spec was revised in May 2024 to the Power ISA v.3.1C spec.<a class="footnote-ref" id="fnref:39" href="#fn:39"><sup>39</sup></a><a class="footnote-ref" id="fnref:40" href="#fn:40"><sup>40</sup></a> </p> Compliant cores <ul><li>All cores that comply with prior versions of the Power ISA</li> <li><a href="/facts/Power10/rJcQsWeR">Power10</a><a class="footnote-ref" id="fnref:41" href="#fn:41"><sup>41</sup></a></li></ul> <h2 id="see-also">See also</h2> <ul><li><a href="/facts/Open-source_computing_hardware/sNbvCc37">Open-source computing hardware</a></li></ul> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>Final draft of Power ISA EULA <a href="https://openpowerfoundation.org/final-draft-of-the-power-isa-eula-released/" target="_blank">https://openpowerfoundation.org/final-draft-of-the-power-isa-eula-released/</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>The Open Power ISA: Architecture Compliancy and Future Foundations <a href="https://www.youtube.com/watch?v=ZGvEpd4vNK0" target="_blank">https://www.youtube.com/watch?v=ZGvEpd4vNK0</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li> <li id="fn:3"><p>Section 2.2 of OPF Power ISA EULA <a href="https://openpowerfoundation.org/final-draft-of-the-power-isa-eula-released/" target="_blank">https://openpowerfoundation.org/final-draft-of-the-power-isa-eula-released/</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li> <li id="fn:4"><p>ELF PP64 ABI <a href="https://refspecs.linuxfoundation.org/ELF/ppc64/PPC-elf64abi.html" target="_blank">https://refspecs.linuxfoundation.org/ELF/ppc64/PPC-elf64abi.html</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li> <li id="fn:5"><p>OpenPOWER EABI v2 <a href="https://openpowerfoundation.org/wp-content/uploads/2016/03/ABI64BitOpenPOWERv1.1_16July2015_pub4.pdf" target="_blank">https://openpowerfoundation.org/wp-content/uploads/2016/03/ABI64BitOpenPOWERv1.1_16July2015_pub4.pdf</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></p></li> <li id="fn:6"><p>Page 18 RISC-V "green card" <a href="https://carrv.github.io/2017/slides/asanovic-riscv-research.pdf" target="_blank">https://carrv.github.io/2017/slides/asanovic-riscv-research.pdf</a> <a href="#fnref:6" class="footnote-back-ref">↩</a></p></li> <li id="fn:7"><p>"Power ISA v.2.03" (PDF). Power.org. 2006-09-29. Archived from the original (PDF) on 2011-07-27. <a href="https://web.archive.org/web/20110727183430/http://www.power.org/resources/downloads/PowerISA_203_Final_Public.pdf" target="_blank">https://web.archive.org/web/20110727183430/http://www.power.org/resources/downloads/PowerISA_203_Final_Public.pdf</a> <a href="#fnref:7" class="footnote-back-ref">↩</a></p></li> <li id="fn:8"><p>"PowerPC Architecture Book, Version 2.02". IBM. 2005-02-24. Archived from the original on 2007-10-18. Retrieved 2007-03-16. <a href="https://web.archive.org/web/20071018025654/http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html" target="_blank">https://web.archive.org/web/20071018025654/http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html</a> <a href="#fnref:8" class="footnote-back-ref">↩</a></p></li> <li id="fn:9"><p>"PowerPC Book E v.1.0" (PDF). IBM. 2002-05-07. Archived (PDF) from the original on 2018-03-10. Retrieved 2007-03-16. <a href="https://www.nxp.com/docs/en/user-guide/BOOK_EUM.pdf?&fsrch=1" target="_blank">https://www.nxp.com/docs/en/user-guide/BOOK_EUM.pdf?&fsrch=1</a> <a href="#fnref:9" class="footnote-back-ref">↩</a></p></li> <li id="fn:10"><p>"Power ISA Version 2.04" (PDF). Power.org. 2007-06-12. Archived from the original (PDF) on 2007-09-27. Retrieved 2007-06-14. <a href="https://web.archive.org/web/20070927235845/http://www.power.org/resources/downloads/PowerISA_Public.pdf" target="_blank">https://web.archive.org/web/20070927235845/http://www.power.org/resources/downloads/PowerISA_Public.pdf</a> <a href="#fnref:10" class="footnote-back-ref">↩</a></p></li> <li id="fn:11"><p>"Power ISA Version 2.05". Power.org. 2007-10-23. Archived from the original on 2012-11-24. Retrieved 2007-12-18. <a href="https://web.archive.org/web/20121124005736/https://www.power.org/technology-introduction/standards-specifications/" target="_blank">https://web.archive.org/web/20121124005736/https://www.power.org/technology-introduction/standards-specifications/</a> <a href="#fnref:11" class="footnote-back-ref">↩</a></p></li> <li id="fn:12"><p>"Power.org Debuts Specification Advances and New Services At Power Architecture Developer Conference" (Press release). Power.org. 2007-09-24. Archived from the original on 2007-10-12. Retrieved 2007-09-24. <a href="https://web.archive.org/web/20071012121931/http://www.power.org/news/pr/view?item_key=20eea4d0ce638d7641d7d04d529d9369fee9e280" target="_blank">https://web.archive.org/web/20071012121931/http://www.power.org/news/pr/view?item_key=20eea4d0ce638d7641d7d04d529d9369fee9e280</a> <a href="#fnref:12" class="footnote-back-ref">↩</a></p></li> <li id="fn:13"><p>"Power ISA Version 2.06 Revision B". Power.org. 2010-07-23. Archived from the original on 2012-11-24. Retrieved 2011-02-12. <a href="https://web.archive.org/web/20121124005736/https://www.power.org/technology-introduction/standards-specifications/" target="_blank">https://web.archive.org/web/20121124005736/https://www.power.org/technology-introduction/standards-specifications/</a> <a href="#fnref:13" class="footnote-back-ref">↩</a></p></li> <li id="fn:14"><p>"Workload acceleration with the IBM POWER vector-scalar architecture". IBM. 2016-03-01. Retrieved 2017-05-02. <a href="https://www.researchgate.net/publication/299472451" target="_blank">https://www.researchgate.net/publication/299472451</a> <a href="#fnref:14" class="footnote-back-ref">↩</a></p></li> <li id="fn:15"><p>"Power ISA Version 2.06 Revision B". Power.org. 2010-07-23. Archived from the original on 2012-11-24. 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