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Massively parallel processor array
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<h2 id="architecture">Architecture</h2> <p>MPPA is a <a href="/facts/Multiple_instruction,_multiple_data/MA3orFRh">MIMD</a> (Multiple Instruction streams, Multiple Data) architecture, with <a href="/facts/Distributed_memory/AxVfko1b">distributed memory</a> accessed locally, not shared globally. Each processor is strictly encapsulated, accessing only its own code and memory. Point-to-point communication between processors is directly realized in the configurable interconnect.<a class="footnote-ref" id="fnref:1" href="#fn:1"><sup>1</sup></a> </p><p>The MPPA's massive parallelism and its distributed memory MIMD architecture distinguishes it from <a href="/facts/Multi-core_(computing)/ABNb65hQ">multicore</a> and <a href="/facts/Manycore_processor/ozoxeNzT">manycore</a> architectures, which have fewer processors and an <a href="/facts/Symmetric_multiprocessing/T9CahUsN">SMP</a> or other <a href="/facts/Shared_memory_architecture/zmpH7WuV">shared memory</a> architecture, mainly intended for general-purpose computing. It's also distinguished from <a href="/facts/GPGPU/roBwsPY2">GPGPUs</a> with <a href="/facts/Single_instruction,_multiple_data/gQHWQSpo">SIMD</a> architectures, used for <a href="/facts/High-performance_computing/HT9NwGAN">HPC</a> applications.<a class="footnote-ref" id="fnref:2" href="#fn:2"><sup>2</sup></a> </p> <h2 id="programming">Programming</h2> <p>An MPPA application is developed by expressing it as a hierarchical <a href="/facts/Block_diagram/PljzAqq6">block diagram</a> or <a href="/facts/Workflow/Ig8zvxF2">workflow</a>, whose basic objects run in parallel, each on their own processor. Likewise, large data objects may be broken up and distributed into local memories with parallel access. Objects communicate over a parallel structure of dedicated channels. The objective is to maximize aggregate throughput while minimizing local latency, optimizing performance and efficiency. An MPPA's <a href="/facts/Model_of_computation/nJr8mHSI">model of computation</a> is similar to a <a href="/facts/Kahn_process_network/LQcsRIrA">Kahn process network</a> or <a href="/facts/Communicating_sequential_processes/bzKGnJ50">communicating sequential processes</a> (CSP).<a class="footnote-ref" id="fnref:3" href="#fn:3"><sup>3</sup></a> </p> <h2 id="applications">Applications</h2> <p>MPPAs are used in high-performance <a href="/facts/Embedded_system/a4muX1wU">embedded systems</a> and <a href="/facts/Hardware_acceleration/ej5sM7hB">hardware acceleration</a> of <a href="/facts/Desktop_computer/edFPINdK">desktop computer</a> and <a href="/facts/Server_(computing)/dEaYFD7r">server</a> applications, such as <a href="/facts/Video_compression/gMFuY4FT">video compression</a>,<a class="footnote-ref" id="fnref:4" href="#fn:4"><sup>4</sup></a><a class="footnote-ref" id="fnref:5" href="#fn:5"><sup>5</sup></a> <a href="/facts/Image_processing/zenalNCf">image processing</a>,<a class="footnote-ref" id="fnref:6" href="#fn:6"><sup>6</sup></a> <a href="/facts/Medical_imaging/pL6JyJEp">medical imaging</a>, <a href="/facts/Network_processing/SW5Lv8UM">network processing</a>, <a href="/facts/Software-defined_radio/k7qLq1mu">software-defined radio</a> and other compute-intensive streaming media applications, which otherwise would use <a href="/facts/FPGA/M8LSGcAU">FPGA</a>, <a href="/facts/Digital_signal_processor/YuBXweos">DSP</a> and/or <a href="/facts/Application-specific_integrated_circuit/YGUXpX50">ASIC</a> chips. </p> <h2 id="examples">Examples</h2> <p>MPPAs developed in companies include ones designed at: <a href="/facts/Ambric/esGgccfU">Ambric</a>, <a href="/facts/PicoChip/LEhWDMG1">PicoChip</a>, <a href="/facts/Intel/SMF0gJJX">Intel</a>,<a class="footnote-ref" id="fnref:7" href="#fn:7"><sup>7</sup></a> IntellaSys, GreenArrays, <a href="/facts/ASOCS/JPauPtlw">ASOCS</a>, <a href="/facts/Tilera/hJNRnFzw">Tilera</a>, <a href="/facts/Kalray/I59JrMsS">Kalray</a>, Coherent Logix, <a href="/facts/Tabula_(company)/ccUUMJrB">Tabula</a>, and <a href="/facts/Adapteva/AcrgoDAm">Adapteva</a>. Aspex (Ericsson) Linedancer differs in that it was a Massive wide <i>SIMD</i> Array rather than an MPPA. Strictly speaking it could qualify as <a href="/facts/Single_Instruction_Multiple_Threads/kRaRt8NX">SIMT</a> due to all 4096 of the 3,000 gate cores having its own Content-Addressable Memory.<a class="footnote-ref" id="fnref:8" href="#fn:8"><sup>8</sup></a><a class="footnote-ref" id="fnref:9" href="#fn:9"><sup>9</sup></a> </p><p>Fabricated MPPAs developed in universities include: 36-core<a class="footnote-ref" id="fnref:10" href="#fn:10"><sup>10</sup></a> and 167-core<a class="footnote-ref" id="fnref:11" href="#fn:11"><sup>11</sup></a> <a href="/facts/Asynchronous_Array_of_Simple_Processors/beVk7CXa">Asynchronous Array of Simple Processors (AsAP)</a> arrays from the <a href="/facts/University_of_California,_Davis/LTCyhaP5">University of California, Davis</a>, 16-core RAW<a class="footnote-ref" id="fnref:12" href="#fn:12"><sup>12</sup></a> from <a href="/facts/MIT/Xk49vNA8">MIT</a>, and 16-core<a class="footnote-ref" id="fnref:13" href="#fn:13"><sup>13</sup></a> and 24-core<a class="footnote-ref" id="fnref:14" href="#fn:14"><sup>14</sup></a> arrays from <a href="/facts/Fudan_University/hUdkzJBg">Fudan University</a>. </p><p>The Chinese <a href="/facts/Sunway_(processor)/0nrQhGzu">Sunway</a> project developed their own 260-core <a href="/facts/SW26010/g8xjmW9I">SW26010</a> manycore chip for the <a href="/facts/TaihuLight/7TLEatpK">TaihuLight</a> supercomputer, which is as of 2016 the world's fastest supercomputer.<a class="footnote-ref" id="fnref:15" href="#fn:15"><sup>15</sup></a><a class="footnote-ref" id="fnref:16" href="#fn:16"><sup>16</sup></a> </p><p>Anton 3 processors, designed by <a href="/facts/D._E._Shaw_Research/FgujNE8M">D. E. Shaw Research</a> for <a href="/facts/Molecular_dynamics/yR3DNt6U">molecular dynamics</a> simulations, contain arrays of 576 processors arranged in a 12×24 tiled grid of pairs of cores; a routed network links these tiles together and extends off-chip to other nodes in a full system.<a class="footnote-ref" id="fnref:17" href="#fn:17"><sup>17</sup></a><a class="footnote-ref" id="fnref:18" href="#fn:18"><sup>18</sup></a> </p> <h2 id="see-also">See also</h2> <ul><li><a href="/facts/Manycore_processor/ozoxeNzT">Manycore processor</a></li> <li><a href="/facts/AI_accelerator/k0QuXHIb">AI accelerator</a></li> <li><a href="/facts/Asynchronous_array_of_simple_processors/beVk7CXa">Asynchronous array of simple processors</a></li> <li><a href="/facts/SW26010/g8xjmW9I">SW26010</a></li> <li><a href="/facts/Array_processor/nYAsIKT0">Array processor</a></li></ul> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>Mike Butts, "Synchronization through Communication in a Massively Parallel Processor Array", IEEE Micro, vol. 27, no. 5, September/October 2007, IEEE Computer Society <a href="/wiki/IEEE_Computer_Society" target="_blank">/wiki/IEEE_Computer_Society</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>Mike Butts, "Multicore and Massively Parallel Platforms and Moore's Law Scalability", Proceedings of the Embedded Systems Conference - Silicon Valley, April 2008 <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li> <li id="fn:3"><p>Mike Butts, Brad Budlong, Paul Wasson, Ed White, "Reconfigurable Work Farms on a Massively Parallel Processor Array", Proceedings of FCCM, April 2008, IEEE Computer Society <a href="/w/index.php?title=FCCM&action=edit&redlink=1" target="_blank">/w/index.php?title=FCCM&action=edit&redlink=1</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li> <li id="fn:4"><p>Laurent Bonetto, "Massively parallel processing arrays (MPPAs) for embedded HD video and imaging (Part 1)", Video/Imaging DesignLine, May 16, 2008 http://www.eetimes.com/document.asp?doc_id=1273823 <a href="http://www.eetimes.com/document.asp?doc_id=1273823" target="_blank">http://www.eetimes.com/document.asp?doc_id=1273823</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li> <li id="fn:5"><p>Laurent Bonetto, "Massively parallel processing arrays (MPPAs) for embedded HD video and imaging (Part 2)", Video/Imaging DesignLine, July 18, 2008 http://www.eetimes.com/document.asp?doc_id=1273830 <a href="http://www.eetimes.com/document.asp?doc_id=1273830" target="_blank">http://www.eetimes.com/document.asp?doc_id=1273830</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></p></li> <li id="fn:6"><p>Paul Chen, "Multimode sensor processing using Massively Parallel Processor Arrays (MPPAs)", Programmable Logic DesignLine, March 18, 2008 http://www.pldesignline.com/howto/206904379 <a href="http://www.pldesignline.com/howto/206904379" target="_blank">http://www.pldesignline.com/howto/206904379</a> <a href="#fnref:6" class="footnote-back-ref">↩</a></p></li> <li id="fn:7"><p>Vangal, Sriram R., Jason Howard, Gregory Ruhl, Saurabh Dighe, Howard Wilson, James Tschanz, David Finan et al. "An 80-tile sub-100-w teraflops processor in 65-nm cmos." Solid-State Circuits, IEEE Journal of 43, no. 1 (2008): 29-41. <a href="#fnref:7" class="footnote-back-ref">↩</a></p></li> <li id="fn:8"><p>Krikelis, A. (1990). "Artificial Neural Network on a Massively Parallel Associative Architecture". International Neural Network Conference. p. 673. doi:10.1007/978-94-009-0643-3_39. ISBN 978-0-7923-0831-7. <a href="978-0-7923-0831-7" target="_blank">978-0-7923-0831-7</a> <a href="#fnref:8" class="footnote-back-ref">↩</a></p></li> <li id="fn:9"><p>https://core.ac.uk/download/pdf/25268094.pdf [bare URL PDF] <a href="https://core.ac.uk/download/pdf/25268094.pdf" target="_blank">https://core.ac.uk/download/pdf/25268094.pdf</a> <a href="#fnref:9" class="footnote-back-ref">↩</a></p></li> <li id="fn:10"><p>Yu, Zhiyi, Michael Meeuwsen, Ryan Apperson, Omar Sattari, Michael Lai, Jeremy Webb, Eric Work, Tinoosh Mohsenin, Mandeep Singh, and Bevan Baas. "An asynchronous array of simple processors for DSP applications." In IEEE International Solid-State Circuits Conference,(ISSCC’06), vol. 49, pp. 428-429. 2006 <a href="#fnref:10" class="footnote-back-ref">↩</a></p></li> <li id="fn:11"><p>Truong, Dean, Wayne Cheng, Tinoosh Mohsenin, Zhiyi Yu, Toney Jacobson, Gouri Landge, Michael Meeuwsen et al. "A 167-processor 65 nm computational platform with per-processor dynamic supply voltage and dynamic clock frequency scaling." In Symposium on VLSI Circuits, pp. 22-23. 2008 <a href="#fnref:11" class="footnote-back-ref">↩</a></p></li> <li id="fn:12"><p>Michael Bedford Taylor, Jason Kim, Jason Miller, David Wentzlaff, Fae Ghodrat, Ben Greenwald, Henry Hoffmann, Paul Johnson, Walter Lee, Arvind Saraf, Nathan Shnidman, Volker Strumpen, Saman Amarasinghe, and Anant Agarwal, "A 16-issue multiple-program-counter microprocessor with point-to-point scalar operand network," Proceedings of the IEEE International Solid-State Circuits Conference, February 2003 <a href="#fnref:12" class="footnote-back-ref">↩</a></p></li> <li id="fn:13"><p>Yu, Zhiyi, Kaidi You, Ruijin Xiao, Heng Quan, Peng Ou, Yan Ying, Haofan Yang, and Xiaoyang Zeng. "An 800MHz 320mW 16-core processor with message-passing and shared-memory inter-core communication mechanisms." In Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International, pp. 64-66. IEEE, 2012. <a href="#fnref:13" class="footnote-back-ref">↩</a></p></li> <li id="fn:14"><p>Ou, Peng, Jiajie Zhang, Heng Quan, Yi Li, Maofei He, Zheng Yu, Xueqiu Yu et al. "A 65nm 39GOPS/W 24-core processor with 11 Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution array." In Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International, pp. 56-57. IEEE, 2013. <a href="#fnref:14" class="footnote-back-ref">↩</a></p></li> <li id="fn:15"><p>Dongarra, Jack (June 20, 2016). "Report on the Sunway TaihuLight System" (PDF). www.netlib.org. Retrieved June 20, 2016. <a href="http://www.netlib.org/utk/people/JackDongarra/PAPERS/sunway-report-2016.pdf" target="_blank">http://www.netlib.org/utk/people/JackDongarra/PAPERS/sunway-report-2016.pdf</a> <a href="#fnref:15" class="footnote-back-ref">↩</a></p></li> <li id="fn:16"><p>Fu, Haohuan; Liao, Junfeng; Yang, Jinzhe; et al. (2016). "The Sunway TaihuLight Supercomputer: System and Applications". Sci. China Inf. Sci. 59 (7). doi:10.1007/s11432-016-5588-7. <a href="https://doi.org/10.1007%2Fs11432-016-5588-7" target="_blank">https://doi.org/10.1007%2Fs11432-016-5588-7</a> <a href="#fnref:16" class="footnote-back-ref">↩</a></p></li> <li id="fn:17"><p>Shaw, David E.; Adams, Peter J.; Azaria, Asaph; Bank, Joseph A.; Batson, Brannon; Bell, Alistair; Bergdorf, Michael; Bhatt, Jhanvi; Butts, J. Adam; Correia, Timothy; Dirks, Robert M.; Dror, Ron O.; Eastwood, Michael P.; Edwards, Bruce; Even, Amos (2021-11-14). "Anton 3". Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis. St. Louis Missouri: ACM. pp. 1–11. doi:10.1145/3458817.3487397. ISBN 978-1-4503-8442-1. S2CID 239036976. <a href="978-1-4503-8442-1" target="_blank">978-1-4503-8442-1</a> <a href="#fnref:17" class="footnote-back-ref">↩</a></p></li> <li id="fn:18"><p>Adams, Peter J.; Batson, Brannon; Bell, Alistair; Bhatt, Jhanvi; Butts, J. Adam; Correia, Timothy; Edwards, Bruce; Feldmann, Peter; Fenton, Christopher H.; Forte, Anthony; Gagliardo, Joseph; Gill, Gennette; Gorlatova, Maria; Greskamp, Brian; Grossman, J.P. (2021-08-22). "The ΛNTON 3 ASIC: A Fire-Breathing Monster for Molecular Dynamics Simulations". 2021 IEEE Hot Chips 33 Symposium (HCS). Palo Alto, CA, USA: IEEE. pp. 1–22. doi:10.1109/HCS52781.2021.9567084. ISBN 978-1-6654-1397-8. S2CID 239039245. <a href="978-1-6654-1397-8" target="_blank">978-1-6654-1397-8</a> <a href="#fnref:18" class="footnote-back-ref">↩</a></p></li> </ol>