VHDL-AMS

<h2 id="code-example">Code example</h2>
<p>In VHDL-AMS, a design consists at a minimum of an <i>entity</i> which describes the interface and an <i>architecture</i> which contains the actual implementation. In addition, most designs import library modules. Some designs also contain multiple architectures and <i>configurations</i>.
</p><p>A simple ideal <a href="/facts/Diode/JyaoyGnk">diode</a> in VHDL-AMS would look something like this:
</p>
library IEEE;
use IEEE.math_real.all;
use IEEE.electrical_systems.all;

-- this is the entity
entity DIODE is
   generic (iss : current := 1.0e-14);   
   port (terminal anode, cathode : electrical);      
end entity DIODE;

architecture IDEAL of DIODE is
  quantity v across i through anode to cathode;
  constant vt : voltage := 0.0258;     
begin

i == iss * (exp(v/vt) - 1.0);

end architecture IDEAL;

<h2 id="vhdl-ams-simulators">VHDL-AMS Simulators</h2>
<ul><li><a href="/facts/ANSYS/46AYvV7W">ANSYS</a> Simplorer</li>
<li><a href="/facts/Cadence_Design_Systems/6pTzpgFc">Cadence</a> Virtuoso AMS Designer</li>
<li><a href="/facts/Dolphin_Integration/SbY9zYvf">Dolphin Integration</a> SMASH</li>
<li><a href="/facts/Mentor_Graphics/EAs59CSJ">Mentor Graphics</a> Questa ADMS</li>
<li>Mentor Graphics SystemVision</li>
<li><a href="/facts/Synopsys/Szv1V36J">Synopsys</a> SaberRD</li></ul>

<h2 id="see-also">See also</h2>
<ul><li><a href="/facts/Verilog-AMS/ty55eeHu">Verilog-AMS</a>, the Analog and Mixed Signal derivative of the <a href="/facts/Verilog/efVqbKXg">Verilog</a> hardware description language</li>
<li><a href="/facts/VHSIC_hardware_description_language/H6Exdjfs">VHDL</a></li>
<li><a href="/facts/Electronic_design_automation/o4la3fmX">Electronic design automation</a></li>
<li><a href="/facts/Very-large-scale_integration/l1Wgqr27">Very-large-scale integration</a></li>
<li><a href="/facts/Modelica/pjWEmtEL">Modelica</a>, a language for modeling physical systems</li></ul>

<h2 id="references">References</h2>

<ol>
<li id="fn:1"><p>Christen E., Bakalar K.,"VHDL-AMS-a hardware description language for analog and mixed-signal applications", Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on] Volume 46,  Issue 10,  Oct. 1999, pp. 1263 - 1272. <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li>
</ol>

VHDL-AMS open-in-new

VHDL-AMS