Long mode

<h2 id="overview">Overview</h2>
<p>An x86-64 processor acts identically to an <a href="/facts/IA-32/7yTv1aHH">IA-32</a> processor when running in real mode or protected mode, which are supported modes when the processor is <i>not</i> in long mode.
</p><p>A bit in the <a href="/facts/CPUID/BdbdpdgB">CPUID</a> extended attributes field informs programs in real or protected modes if the processor can go to long mode, which allows a program to detect an x86-64 processor. This is similar to the CPUID attributes bit that <a href="/facts/Intel/SMF0gJJX">Intel</a> <a href="/facts/IA-64/m6egpGno">IA-64</a> processors use to allow programs to detect if they are running under IA-32 emulation. 
</p><p>With a computer running legacy <a href="/facts/BIOS/AYYPUogS">BIOS</a>, the BIOS and the <a href="/facts/Boot_loader/6sNpcLMK">boot loader</a> run in <a href="/facts/Real_mode/wfU8vfjn">real mode</a>. After execution passes to an <a href="/facts/Operating_system_kernel/uEj4U3Rz">operating system kernel</a> which supports x86-64, the kernel verifies CPU support for long mode and then executes the instructions to enter it. With a computer running <a href="/facts/UEFI/w86VGmy2">UEFI</a>, the UEFI firmware (except CSM and legacy <a href="/facts/Option_ROM/NSra8Rl3">Option ROM</a>), any UEFI boot loader, and the operating system kernel all run in Long mode.
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<h2 id="memory-limitations">Memory limitations</h2>
<p class="note">See also: <a href="/facts/X86-64_virtual_address_space/cyWvUFlP">x86-64 virtual address space</a></p>
<p>While register sizes have increased to 64 bits from the previous <a href="/facts/X86_architecture/Kypq5fgu">x86 architecture</a>, <a href="/facts/Memory_addressing/7EsUmbea">memory addressing</a> has not yet been increased to the full 64 bits. For the time being, it is impractical to equip computers with sufficient memory to require a full 64 bits. As long as that remains the case, load/store unit(s), <a href="/facts/CPU_cache/x8BYFcdv">cache</a> tags, <a href="/facts/Memory_management_unit/tJQtAQzI">MMUs</a> and <a href="/facts/Translation_lookaside_buffer/vvwGkfvD">TLBs</a> can be simplified without any loss of usable memory. Despite this limitation, software is programmed using full 64-bit <a href="/facts/Pointer_(computer_programming)/fPoNzy9b">pointers</a>, and will therefore be able to use progressively larger address spaces as they become supported by future processors and operating systems.
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<h3>Current limits</h3>
<p>The first CPUs implementing the x86-64 architecture, namely the AMD <a href="/facts/Athlon_64/3JLpVnQd">Athlon 64</a> / <a href="/facts/Opteron/IF1ueyIJ">Opteron</a> (K8) CPUs, had <a href="/facts/48-bit/KTsN8bB1">48-bit</a> <a href="/facts/Virtual_address/ILxbMjgv">virtual</a><a class="footnote-ref" id="fnref:1" href="#fn:1"><sup>1</sup></a>: 129–130  and 40-bit <a href="/facts/Physical_address/G01PUI6A">physical addressing</a>.<a class="footnote-ref" id="fnref:2" href="#fn:2"><sup>2</sup></a>: 4 
</p><p>The virtual address space of these processors is divided into two 47-bit regions, one starting at the lowest possible address, the other extending down from the largest. Attempting to use addresses falling outside this range will cause a <a href="/facts/General_protection_fault/Q92zbKIo">general protection fault</a>.
</p><p>The limit of physical addressing constrains how much installed <a href="/facts/Random-access_memory/DuD4bxh6">RAM</a> is able to be accessed by the computer. On a <a href="/facts/CcNUMA/MpmN5mN0">ccNUMA</a> <a href="/facts/Multiprocessor/aDCfehDQ">multiprocessor</a> system (Opteron) this includes the memory which is installed in the remote nodes, because the CPUs can directly address (and cache) all memory regardless if it is on the home node or remote. The 1 <a href="/facts/Terabyte/BNHUp9Qq">TB</a> limit (40-bit) for physical memory for the K8 is huge by typical personal computer standards, but might have been a limitation for use in supercomputers. Consequently, the <a href="/facts/AMD_K10/2hQAazep">K10</a> (or "10h") <a href="/facts/Microarchitecture/NFRd4NUL">microarchitecture</a> implements 48-bit physical addresses and so can address up to 256 <a href="/facts/Terabyte/BNHUp9Qq">TB</a> of RAM.<a class="footnote-ref" id="fnref:3" href="#fn:3"><sup>3</sup></a>
</p><p>When there is need, the microarchitecture can be expanded step by step without side-effects from software and simultaneously save cost with its implementation. For future expansion, the architecture supports expanding virtual address space to 64 bits, and physical memory addressing to 52 bits (limited by the <a href="/facts/Page_table/0IBU5cwg">page table</a> entry format).<a class="footnote-ref" id="fnref:4" href="#fn:4"><sup>4</sup></a> This would allow the processor to address 264 bytes (16 <a href="/facts/Exabyte/BNHUp9Qq">exabytes</a>) of virtual address space and 252 bytes (4 <a href="/facts/Petabyte/BNHUp9Qq">petabytes</a>) of physical address space.
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<h2 id="see-also">See also</h2>
<ul><li><a href="/facts/X86-64/cyWvUFlP">x86-64</a></li>
<li><a href="/facts/64-bit_compatibility_mode/cyWvUFlP">64-bit compatibility mode</a></li></ul>

<h2 id="external-links">External links</h2>
<ul><li>Zeichick, Alan (2003-12-03). <a href="https://web.archive.org/web/20120214231920/http://developer.amd.com/pages/123200367.aspx">"Platforms and Tools for the AMD Athlon 64 Processor"</a>. Developer. AMD. Archived from <a href="http://developer.amd.com/pages/123200367.aspx">the original</a> on 2012-02-14. A guide to the new features of long mode</li>
<li>Chourdakis, Michael (2015-05-21). <a href="http://www.codeproject.com/Articles/45788/The-Real-Protected-Long-mode-assembly-tutorial-for">"The Real, Protected, Long mode assembly tutorial for PCs"</a>. <i>Code Project</i>.</li></ul>

<h2 id="references">References</h2>

<ol>
<li id="fn:1"><p>"AMD64 Architecture Programmer's Manual Volume 2: System Programming" (PDF). 2016. Retrieved 2015-04-09. <a href="http://support.amd.com/TechDocs/24593.pdf" target="_blank">http://support.amd.com/TechDocs/24593.pdf</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li>
<li id="fn:2"><p>"AMD64 Architecture Programmer's Manual Volume 2: System Programming" (PDF). 2016. Retrieved 2015-04-09. <a href="http://support.amd.com/TechDocs/24593.pdf" target="_blank">http://support.amd.com/TechDocs/24593.pdf</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li>
<li id="fn:3"><p>"BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h Processors" (PDF). p. 30. Retrieved 2015-04-09. Physical address space increased to 48 bits. <a href="http://support.amd.com/TechDocs/31116.pdf" target="_blank">http://support.amd.com/TechDocs/31116.pdf</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li>
<li id="fn:4"><p>AMD 2016, p. 24: "The AMD64 architecture enhances this support to allow translation of 64-bit virtual addresses into 52-bit physical addresses, although processor implementations can support smaller virtual-address and physical-address spaces." - "AMD64 Architecture Programmer's Manual Volume 2: System Programming" (PDF). 2016. Retrieved 2015-04-09. <a href="http://support.amd.com/TechDocs/24593.pdf" target="_blank">http://support.amd.com/TechDocs/24593.pdf</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li>
</ol>

Long mode open-in-new

Long mode