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Beyond CMOS
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<h2 id="comparisons-of-technology">Comparisons of technology</h2> <p>About 2010 the Nanoelectronic Research Initiative (NRI) studied various circuits in various technologies.<a class="footnote-ref" id="fnref:8" href="#fn:8"><sup>8</sup></a> </p><p>Nikonov benchmarked (theoretically) many technologies in 2012,<a class="footnote-ref" id="fnref:9" href="#fn:9"><sup>9</sup></a> and updated it in 2014.<a class="footnote-ref" id="fnref:10" href="#fn:10"><sup>10</sup></a> The 2014 benchmarking included 11 electronic, 8 <a href="/facts/Spintronic/dAWl8rcI">spintronic</a>, 3 orbitronic, 2 <a href="/facts/Ferroelectric/DLVYFNQT">ferroelectric</a>, and 1 <a href="/facts/Straintronics/ctlhoj1e">straintronics</a> technology.<a class="footnote-ref" id="fnref:11" href="#fn:11"><sup>11</sup></a> </p><p>The 2015 <a href="/facts/ITRS_2.0/vD2UyM3h">ITRS 2.0</a> report included a detailed chapter on <i>Beyond CMOS</i>,<a class="footnote-ref" id="fnref:12" href="#fn:12"><sup>12</sup></a> covering RAM and logic gates. </p> <h2 id="some-areas-of-investigation">Some areas of investigation</h2> <ul><li><a href="/facts/Magneto-Electric_Spin-Orbit/QHyutFRt">Magneto-Electric Spin-Orbit</a> logic<a class="footnote-ref" id="fnref:13" href="#fn:13"><sup>13</sup></a></li> <li><a href="/facts/Tunnel_junction/BK3CvrpP">tunnel junction</a> devices, e.g. <a href="/facts/Tunnel_field-effect_transistor/nV2wBq6M">Tunnel field-effect transistor</a><a class="footnote-ref" id="fnref:14" href="#fn:14"><sup>14</sup></a></li> <li><a href="/facts/Indium_antimonide/76EPwVLC">indium antimonide</a> transistors</li> <li><a href="/facts/Carbon_nanotube_field-effect_transistor/EVQmIUak">carbon nanotube FET</a>, e.g. CNT <a href="/facts/Tunnel_field-effect_transistor/nV2wBq6M">Tunnel field-effect transistor</a></li> <li><a href="/facts/Graphene_nanoribbons/Xh4bnMgk">graphene nanoribbons</a></li> <li><a href="/facts/Molecular_electronics/nC056GHG">molecular electronics</a></li> <li><a href="/facts/Spintronics/dAWl8rcI">spintronics</a> — many variants</li> <li><a href="/facts/ARC_Centre_of_Excellence_in_Future_Low-Energy_Electronics_Technologies/gpjvlDcS">future low-energy electronics technologies</a>, ultra-low dissipation conduction paths, including <ul><li><a href="/facts/Topological_insulator/pbrbxG9X">topological materials</a></li> <li><a href="/facts/Polariton_superfluid/cb9MbUgw">exciton superfluids</a></li></ul></li> <li><a href="/facts/Photonics/6UHcPXbq">photonics</a> and <a href="/facts/Optical_computing/aPl6UjC9">optical computing</a></li> <li><a href="/facts/Superconducting_computing/VjdLaVDr">superconducting computing</a> <ul><li><a href="/facts/Rapid_single_flux_quantum/ufw0Ro72">rapid single-flux quantum</a> (RSFQ)</li></ul></li></ul> <h2 id="superconducting-computing-and-rsfq">Superconducting computing and RSFQ</h2> <p><a href="/facts/Superconducting_computing/VjdLaVDr">Superconducting computing</a> includes several beyond-CMOS technologies that use superconducting devices, namely <a href="/facts/Josephson_junctions/2fvcdS8N">Josephson junctions</a>, for electronic signals processing and computing. One variant called <a href="/facts/Rapid_single_flux_quantum/ufw0Ro72">rapid single-flux quantum</a> (RSFQ) logic was considered promising by the NSA in a 2005 technology survey despite the drawback that available superconductors require cryogenic temperatures. More energy-efficient superconducting logic variants have been developed since 2005 and are being considered for use in large scale computing.<a class="footnote-ref" id="fnref:15" href="#fn:15"><sup>15</sup></a><a class="footnote-ref" id="fnref:16" href="#fn:16"><sup>16</sup></a> </p> <h2 id="see-also">See also</h2> <ul><li><a href="/facts/International_Technology_Roadmap_for_Semiconductors/vD2UyM3h">International Technology Roadmap for Semiconductors</a></li> <li><a href="/facts/International_Roadmap_for_Devices_and_Systems/1B04onFY">International Roadmap for Devices and Systems</a></li> <li><a href="/facts/Moore%2527s_law/90CSekhl">Moore's law</a></li> <li><a href="/facts/MOSFET/eTDJT2Km">MOSFET scaling</a></li> <li><a href="/facts/Nanostrain/9JIfJ575">Nanostrain</a>, a project to characterise piezoelectric materials for low power switches</li> <li><a href="/facts/S-PULSE/CoGkPXyv">S-PULSE</a>, the EU Shrink-Path of Ultra-Low Power Superconducting Electronics initiative</li> <li>Probabilistic complementary metal-oxide semiconductor (<a href="/facts/PCMOS/yqSxJrvW">PCMOS</a>)</li></ul> <h2 id="further-reading">Further reading</h2> <ul><li>Banerjee, Niloy (2019-09-03). <a href="https://www.bisinfotech.com/new-door-in-the-beyond-cmos-world/">"New Door in the "Beyond CMOS" World"</a>. <i>BISinfotech</i>. <a href="https://web.archive.org/web/20220513194310/https://www.bisinfotech.com/new-door-in-the-beyond-cmos-world/">Archived</a> from the original on 2022-05-13. Retrieved 2022-05-13.</li> <li>Nikonov, Dmitri E.; <a href="/facts/Ian_A._Young/tYBIywUL">Ian A</a>. (2013–12). "Overview of Beyond-CMOS Devices and a Uniform Methodology for Their Benchmarking". <i>Proceedings of the IEEE</i>. 101 (12): 2498–2533. <a href="/facts/Doi_(identifier)/muM9Etpq">doi</a>:10.1109/jproc.2013.2252317. <a href="/facts/ISSN_(identifier)/DPAflDvU">ISSN</a> 0018-9219.</li> <li>Seabaugh, A.C. and Zhang, Q., 2010. Low-voltage tunnel transistors for beyond CMOS logic. <i>Proceedings of the IEEE</i>, <i>98</i>(12), pp. 2095–2110.</li> <li>Bernstein, K., Cavin, R.K., Porod, W., Seabaugh, A. and Welser, J., 2010. Device and architecture outlook for beyond CMOS switches. <i>Proceedings of the IEEE</i>, <i>98</i>(12), pp. 2169–2184.</li> <li><a href="/facts/Sasikanth_Manipatruni/9qNKUzH1">Sasikanth Manipatruni</a>, Nikonov, D.E. and <a href="/facts/Ian_A._Young/tYBIywUL">Ian A. Young</a>, 2018. Beyond CMOS computing with spin and polarization. <i>Nature Physics</i>, <i>14</i>(4), pp. 338–343.</li> <li>Banerjee, S.K., Register, L.F., Tutuc, E., Basu, D., Kim, S., Reddy, D. and MacDonald, A.H., 2010. Graphene for CMOS and beyond CMOS applications. <i>Proceedings of the IEEE</i>, <i>98</i>(12), pp. 2032–2046.</li> <li>Topaloglu, R.O. and Wong, H.S.P. eds., 2019. <i>Beyond-CMOS technologies for next generation computer design</i>. Berlin/Heidelberg, Germany: Springer.</li> <li><a href="/facts/Sasikanth_Manipatruni/9qNKUzH1">Sasikanth Manipatruni</a>, Nikonov, D.E., Lin, C.C., Gosavi, T.A., Liu, H., Prasad, B., Huang, Y.L., Bonturim, E., Ramesh, R. and Young, I.A., 2019. Scalable energy-efficient magnetoelectric spin–orbit logic. <i>Nature</i>, <i>565</i>(7737), pp. 35–42.</li></ul> <h2 id="external-links">External links</h2> <ul><li><a href="https://web.archive.org/web/20151212172641/http://www.itrs.net/ITRS%201999-2014%20Mtgs%2C%20Presentations%20%26%20Links/2013ITRS/Summary2013.htm">ITRS 2013 edition</a> <ul><li><a href="https://web.archive.org/web/20150920032846/http://www.itrs.net/ITRS%201999-2014%20Mtgs%2C%20Presentations%20%26%20Links/2013ITRS/2013Chapters/2013ERD_Summary.pdf">EMERGING RESEARCH DEVICES SUMMARY</a></li> <li><a href="https://web.archive.org/web/20150920035944/http://www.itrs.net/ITRS%201999-2014%20Mtgs%2C%20Presentations%20%26%20Links/2013ITRS/2013Chapters/2013PIDS_Summary.pdf">Process Integration, Devices and structures summary</a></li></ul></li></ul> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>"Extending the road beyond CMOS. Hutchby 2002" (PDF). Archived (PDF) from the original on 2022-12-06. Retrieved 2023-04-16. <a href="https://web.stanford.edu/class/ee311/NOTES/Hutchby_ProcIEEE03.pdf" target="_blank">https://web.stanford.edu/class/ee311/NOTES/Hutchby_ProcIEEE03.pdf</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>Nikonov, Dmitri E.; Young, Ian A. (September 2012). "Overview of Beyond-CMOS Devices and A Uniform Methodology for Their Benchmarking". arXiv:1302.0244 [cond-mat.mes-hall]. <a href="/wiki/ArXiv_(identifier)" target="_blank">/wiki/ArXiv_(identifier)</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li> <li id="fn:3"><p>Bernstein; et al. (2011). "Device and Architecture Outlook for Beyond CMOS Switches". Archived from the original on 2015-02-22. Retrieved 2015-02-22. {{cite journal}}: Cite journal requires |journal= (help) <a href="https://www.fp7-nanotec.eu/content/device-and-architecture-outlook-beyond-cmos-switches-kerry-bernstein-wolfgang-porod-and-jeff" target="_blank">https://www.fp7-nanotec.eu/content/device-and-architecture-outlook-beyond-cmos-switches-kerry-bernstein-wolfgang-porod-and-jeff</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li> <li id="fn:4"><p>"Review of Advanced and Beyond CMOS FET Technologies for Radio Frequency Circuit Design. Carta 2011" (PDF). Archived from the original (PDF) on 2015-02-23. Retrieved 2015-02-23. <a href="https://web.archive.org/web/20150223025752/http://www.mos-ak.org/dresden/publications/T4_Carta_MOS-AK_12.pdf" target="_blank">https://web.archive.org/web/20150223025752/http://www.mos-ak.org/dresden/publications/T4_Carta_MOS-AK_12.pdf</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li> <li id="fn:5"><p>Frank, D.J. (March 2002). "Power-constrained CMOS scaling limits". IBM Journal of Research and Development. 46 (2.3): 235–244. CiteSeerX 10.1.1.84.4043. doi:10.1147/rd.462.0235. <a href="/wiki/CiteSeerX_(identifier)" target="_blank">/wiki/CiteSeerX_(identifier)</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></p></li> <li id="fn:6"><p>"Samsung vows to start 10nm chip production in 2016". 23 May 2015. Archived from the original on 16 July 2015. Retrieved 16 July 2015. <a href="http://www.kitguru.net/components/anton-shilov/samsung-vows-to-start-10nm-chip-production-in-2016-shows-first-wafers/" target="_blank">http://www.kitguru.net/components/anton-shilov/samsung-vows-to-start-10nm-chip-production-in-2016-shows-first-wafers/</a> <a href="#fnref:6" class="footnote-back-ref">↩</a></p></li> <li id="fn:7"><p>"Review of Advanced and Beyond CMOS FET Technologies for Radio Frequency Circuit Design. Carta 2011" (PDF). Archived from the original (PDF) on 2015-02-23. Retrieved 2015-02-23. <a href="https://web.archive.org/web/20150223025752/http://www.mos-ak.org/dresden/publications/T4_Carta_MOS-AK_12.pdf" target="_blank">https://web.archive.org/web/20150223025752/http://www.mos-ak.org/dresden/publications/T4_Carta_MOS-AK_12.pdf</a> <a href="#fnref:7" class="footnote-back-ref">↩</a></p></li> <li id="fn:8"><p>Nikonov, Dmitri E.; Young, Ian A. (September 2012). "Overview of Beyond-CMOS Devices and A Uniform Methodology for Their Benchmarking". arXiv:1302.0244 [cond-mat.mes-hall]. <a href="/wiki/ArXiv_(identifier)" target="_blank">/wiki/ArXiv_(identifier)</a> <a href="#fnref:8" class="footnote-back-ref">↩</a></p></li> <li id="fn:9"><p>Nikonov, Dmitri E.; Young, Ian A. (September 2012). "Overview of Beyond-CMOS Devices and A Uniform Methodology for Their Benchmarking". arXiv:1302.0244 [cond-mat.mes-hall]. <a href="/wiki/ArXiv_(identifier)" target="_blank">/wiki/ArXiv_(identifier)</a> <a href="#fnref:9" class="footnote-back-ref">↩</a></p></li> <li id="fn:10"><p>Nikonov; Young (2015). "Benchmarking of Beyond-CMOS Exploratory – Devices for Logic Integrated Circuits". IEEE Journal on Exploratory Solid-State Computational Devices and Circuits. 1: 3–11. Bibcode:2015IJESS...1....3N. doi:10.1109/JXCDC.2015.2418033. <a href="https://doi.org/10.1109%2FJXCDC.2015.2418033" target="_blank">https://doi.org/10.1109%2FJXCDC.2015.2418033</a> <a href="#fnref:10" class="footnote-back-ref">↩</a></p></li> <li id="fn:11"><p>Nikonov; Young (2015). "Benchmarking of Beyond-CMOS Exploratory – Devices for Logic Integrated Circuits". IEEE Journal on Exploratory Solid-State Computational Devices and Circuits. 1: 3–11. Bibcode:2015IJESS...1....3N. doi:10.1109/JXCDC.2015.2418033. <a href="https://doi.org/10.1109%2FJXCDC.2015.2418033" target="_blank">https://doi.org/10.1109%2FJXCDC.2015.2418033</a> <a href="#fnref:11" class="footnote-back-ref">↩</a></p></li> <li id="fn:12"><p>Beyond CMOS (PDF). International Technology Roadmap for Semiconductors 2.0 (2015 ed.). Archived (PDF) from the original on 2023-04-16. Retrieved 2017-06-16. <a href="https://www.dropbox.com/sh/3jfh5fq634b5yqu/AACxgvNR8zhcTYt2cp2nj0WOa/6_2015%20ITRS%202.0%20Beyond%20CMOS.pdf" target="_blank">https://www.dropbox.com/sh/3jfh5fq634b5yqu/AACxgvNR8zhcTYt2cp2nj0WOa/6_2015%20ITRS%202.0%20Beyond%20CMOS.pdf</a> <a href="#fnref:12" class="footnote-back-ref">↩</a></p></li> <li id="fn:13"><p>Manipatruni, Sasikanth; Nikonov, Dmitri E.; Lin, Chia-Ching; Gosavi, Tanay A.; Liu, Huichu; Prasad, Bhagwati; Huang, Yen-Lin; Bonturim, Everton; Ramesh, Ramamoorthy; Young, Ian A. (2018-12-03). "Scalable energy-efficient magnetoelectric spin–orbit logic". Nature. 565 (7737): 35–42. doi:10.1038/s41586-018-0770-2. ISSN 0028-0836. PMID 30510160. S2CID 256769872. <a href="https://dx.doi.org/10.1038/s41586-018-0770-2" target="_blank">https://dx.doi.org/10.1038/s41586-018-0770-2</a> <a href="#fnref:13" class="footnote-back-ref">↩</a></p></li> <li id="fn:14"><p>Seabaugh (September 2013). "The Tunneling Transistor". IEEE Spectrum. 50 (10). IEEE: 35–62. doi:10.1109/MSPEC.2013.6607013. S2CID 2729197. Archived from the original on 2021-06-29. Retrieved 2023-04-16. <a href="https://spectrum.ieee.org/the-tunneling-transistor" target="_blank">https://spectrum.ieee.org/the-tunneling-transistor</a> <a href="#fnref:14" class="footnote-back-ref">↩</a></p></li> <li id="fn:15"><p>Holmes, D.S.; Ripple, A.L.; Manheimer, M.A. (June 2013). "Energy-efficient superconducting computing—power budgets and requirements". IEEE Trans. Appl. Supercond. 23 (3). 1701610. Bibcode:2013ITAS...2301610H. doi:10.1109/TASC.2013.2244634. S2CID 20374012. Archived from the original on 2022-10-10. Retrieved 2023-04-16. <a href="https://ieeexplore.ieee.org/document/6449287" target="_blank">https://ieeexplore.ieee.org/document/6449287</a> <a href="#fnref:15" class="footnote-back-ref">↩</a></p></li> <li id="fn:16"><p>Holmes, D.S.; Kadin, A.M.; Johnson, M.W. (December 2015). "Superconducting Computing in Large-Scale Hybrid Systems". Computer. 48 (12): 34–42. doi:10.1109/MC.2015.375. S2CID 26578755. Archived from the original on 2022-12-25. Retrieved 2023-04-16. <a href="https://ieeexplore.ieee.org/document/7368011" target="_blank">https://ieeexplore.ieee.org/document/7368011</a> <a href="#fnref:16" class="footnote-back-ref">↩</a></p></li> </ol>