Apollo PRISM

<h2 id="compilers">Compilers</h2>
<p>The <a href="/facts/Compiler/WNfCDFJe">compilers</a> used with the systems were expected to dedicate more time during compilation to making effective use of the registers and cleaning the <a href="/facts/Instruction_(computer_science)/8p8vwUeE">instruction</a> stream.  By doing <a href="/facts/Instruction_scheduling/5GuldkLY">instruction scheduling</a> in the compiler, this design avoided the problems and complexity of dynamic instruction scheduling (where instructions for multiple <a href="/facts/Functional_unit/uvg54JcX">functional units</a> must be selected carefully in order to avoid interdependencies between intermediate values) encountered in <a href="/facts/Superscalar/gPxRAb25">superscalar</a> designs such as <a href="/facts/Digital_Equipment_Corporation/ztxs6keA">Digital Equipment Corporation</a>'s <a href="/facts/DEC_Alpha/4eN7LuXG">Alpha</a>.
</p><p>In some respects, the VLIW design can be thought of as "super-RISCy", as it offloads the instruction selection process to the compiler as well. In the VLIW design, the compiler examines the code and selects instructions that are known to be "safe", and then packages them into longer instruction words. For instance, for a CPU with two functional units, like the PRISM, the compiler would find pairs of safe instructions and stuff them into a single larger word. Inside the CPU, the instructions are simply split apart again, and fed into the selected units.
</p><p>This design minimizes logical changes to the CPU as functional units are added, as the compiler is handling the instruction selection. However, this also ties the compiled code very tightly to the processor design; for instance, if a new generation of the CPU adds additional functional units, all programs running on it must be re-compiled so the compiler can re-arrange the instructions again, perhaps four-wide instead of two-wide. In comparison, a more traditional design like the <a href="/facts/PowerPC/DqmM9y50">PowerPC</a> (PPC) has seen dramatic internal changes, yet code written for the first PPC's will still run without modification on the latest versions. The cost for this is an increasing amount of chip space that has to be dedicated to <a href="/facts/Instruction_scheduling/5GuldkLY">instruction scheduling</a>.
</p><p>The Apollo compilers were the first commercial compilers to use <a href="/facts/Single_static_assignment/HnDHfx6I">single static assignment</a> techniques.
</p>
<h2 id="architectural-features">Architectural features</h2>
<p>PRISM was a "pure" <a href="/facts/32-bit/TDMVce8s">32-bit</a> design, including thirty-two 32-bit <a href="/facts/Integer/PUwwrawx">integer</a> and thirty-two 64-bit <a href="/facts/Floating_point/eIckahxe">floating point</a> registers (overlaid by sixty-four 32-bit registers).  PRISM could dispatch a single integer or one integer and one floating point instruction per <a href="/facts/Clock_signal/9UfTzGHx">clock cycle</a>.  The floating-point instruction could, in turn, combine a floating-point add and multiply in a single instruction.  The compiler attempted to always pair (or triple) instructions up to maintain full use of the internal units, but if it failed to find a safe pair it simply fed in a single integer instruction. PRISM was one of the first designs to include a multiply with add/subtract/truncate in a single (five <a href="/facts/Operand/HSuUzrKz">operand</a>) instruction, so it was often described as a three-issue CPU.
</p>
<h2 id="history">History</h2>
<p>The original PRISM design was introduced in 1988 in the one-to-four-CPU <a href="/facts/Apollo/Domain/qdXLE7E1">Apollo DN10000</a> <a href="/facts/Workstation/h5tK4hTt">workstations</a>. The "DN" in the name refers to "Domain Node", <a href="/facts/Domain/OS/Nzs4bcor">Domain/OS</a> being the <a href="/facts/Unix-like/YAKrAxzd">Unix-like</a> <a href="/facts/Operating_system/8XTuvMh2">operating system</a> used on all of Apollo's machines. Note that PRISM was a multi-chip CPU board, not a single <a href="/facts/Microprocessor/Fx9CaQht">microprocessor</a>; this was fairly common for high-end CPUs at the time.
</p><p>Approximately one thousand DN10000 systems were sold.
</p><p>PRISM II, running at twice the clock speed, was delayed by problems in <a href="/facts/Semiconductor_fabrication/Jd23Mu1z">fabing</a>, and then eventually cancelled after the HP purchase. Nevertheless, several features of the PRISM design were put into later generations of the <a href="/facts/HP-PA/gjDs1HEh">HP-PA</a> architecture, and the two main proponents of the VLIW concept, Intel and HP, later collaborated on the <a href="/facts/Itanium/0wkjSDpe">Itanium</a>.
</p><p>The PRISM was claimed to be the fastest CPU on the market during its short life-span.<a class="footnote-ref" id="fnref:1" href="#fn:1"><sup>1</sup></a> Benchmarking indicated that the speed of the DN10000's CPU was comparable to that of the MIPS M/2000-6, a 20 MHz R3000,<a class="footnote-ref" id="fnref:2" href="#fn:2"><sup>2</sup></a> but the DN10000 as a system had around twice the performance of the MIPS M/2000-6.<a class="footnote-ref" id="fnref:3" href="#fn:3"><sup>3</sup></a> In comparison with common RISC designs of the era, the PRISM was effectively two CPUs in one, making it roughly double the performance of a RISC CPU running at the same clock speed.
</p>
<h2 id="contemporary-competitors">Contemporary competitors</h2>
<p>Although the <a href="/facts/Intel_i860/e2wRyFV1">Intel i860</a> also used a VLIW (or properly LIW in both cases, as two is not "very" long), extracting performance from the i860 proved notoriously difficult, and in practice the PRISM was much faster.
</p><p><a href="/facts/Digital_Equipment_Corporation/ztxs6keA">Digital Equipment Corporation</a> also engineered a <a href="/facts/DEC_PRISM/qsRxJ49P">RISC chip named PRISM</a> during the same era, but that project was canceled in 1988, and never entered production.
</p>

<ul><li><a href="https://web.archive.org/web/20120308083039/http://jbayko.sasktelwebsite.net/cpu5.html">The Great CPU List, Section 5, Part II: Apollo PRISM - Superworkstation</a></li></ul>

<h2 id="references">References</h2>

<ol>
<li id="fn:1"><p>Bayko, John (May 2003). "Section 5, Part II: Apollo PRISM - Superworkstation". Great Microprocessors of the Past and Present. Retrieved 8 March 2023. <a href="http://www.landley.net/history/mirror/tech/processors/cpu5.html#Sec5Part2" target="_blank">http://www.landley.net/history/mirror/tech/processors/cpu5.html#Sec5Part2</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li>
<li id="fn:2"><p>M/2000 RISComputer. MIPS Computer Systems. p. 10. Retrieved 8 March 2023. <a href="https://archive.org/details/bitsavers_mipsbrochu_6758994/page/n10/mode/1up" target="_blank">https://archive.org/details/bitsavers_mipsbrochu_6758994/page/n10/mode/1up</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li>
<li id="fn:3"><p>"Benchmarks: speed versus cost". IEEE Micro. April 1989. p. 83. Retrieved 8 March 2023. <a href="https://archive.org/details/ieee_micro_v9n2_apr_89/page/n86/mode/1up" target="_blank">https://archive.org/details/ieee_micro_v9n2_apr_89/page/n86/mode/1up</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li>
</ol>

Apollo PRISM open-in-new

Apollo PRISM