Stub Series Terminated Logic

<h2 id="see-also">See also</h2>
<ul><li><a href="/facts/High-Speed_Transceiver_Logic/HAhn3cEc">High-Speed Transceiver Logic</a> - HSTL</li></ul>

<h2 id="external-links">External links</h2>
<p>JEDEC homepage links; require (free) login:
</p>
<ul><li><a href="http://www.jedec.org/sites/default/files/docs/JESD8-9B.pdf">JEDEC SSTL_2 Standard (JESD8-9B)</a></li>
<li><a href="http://www.jedec.org/sites/default/files/docs/JESD8-15A.pdf">JEDEC SSTL_18 Standard (JESD8-15A)</a></li></ul>

<h2 id="references">References</h2>

<ol>
<li id="fn:1"><p>Jaci Chang Design Considerations for the DDR3 Memory Sub-system. Jedex, 2004, p. 4. http://www.jedex.org/images/pdf/samsung%20-%20jaci_chang.pdf <a href="http://www.jedex.org/images/pdf/samsung%20-%20jaci_chang.pdf" target="_blank">http://www.jedex.org/images/pdf/samsung%20-%20jaci_chang.pdf</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li>
<li id="fn:2"><p>Tom Granberg Handbook of Digital Techniques for High-Speed Digital Design.  Pearson Education, 2004, p. 160-161. <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li>
</ol>

Stub Series Terminated Logic open-in-new

Stub Series Terminated Logic