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<h2 id="examples">Examples</h2> <p>An example of MIMD system is <a href="/facts/Xeon_Phi/Fv5dhyKc">Intel Xeon Phi</a>, descended from <a href="/facts/Larrabee_(microarchitecture)/SqD9e2Kj">Larrabee</a> microarchitecture.<a class="footnote-ref" id="fnref:1" href="#fn:1"><sup>1</sup></a> These processors have multiple processing cores (up to 61 as of 2015) that can execute different instructions on different data. </p><p>Most parallel computers, as of 2013, are MIMD systems.<a class="footnote-ref" id="fnref:2" href="#fn:2"><sup>2</sup></a> </p> <h2 id="shared-memory-model">Shared memory model</h2> <p>In shared memory model the processors are all connected to a "globally available" memory, via either <a href="/facts/Software/RP79lVSW">software</a> or hardware means. The <a href="/facts/Operating_system/8XTuvMh2">operating system</a> usually maintains its <a href="/facts/Memory_coherence/eJD9GntF">memory coherence</a>.<a class="footnote-ref" id="fnref:3" href="#fn:3"><sup>3</sup></a> </p><p>From a programmer's point of view, this memory model is better understood than the distributed memory model. Another advantage is that memory coherence is managed by the operating system and not the written program. Two known disadvantages are: scalability beyond thirty-two processors is difficult, and the shared memory model is less flexible than the distributed memory model.<a class="footnote-ref" id="fnref:4" href="#fn:4"><sup>4</sup></a> </p><p>There are many examples of shared memory (multiprocessors): UMA (<a href="/facts/Uniform_memory_access/8o4ILNRr">uniform memory access</a>), COMA (<a href="/facts/Cache-only_memory_architecture/qQea99Gn">cache-only memory access</a>).<a class="footnote-ref" id="fnref:5" href="#fn:5"><sup>5</sup></a> </p> <h3>Bus-based</h3> <p>MIMD machines with shared memory have processors which share a common, central memory. In the simplest form, all processors are attached to a bus which connects them to memory. This means that every machine with shared memory shares a specific CM, common bus system for all the clients. </p><p>For example, if we consider a bus with clients A, B, C connected on one side and P, Q, R connected on the opposite side, any one of the clients will communicate with the other by means of the bus interface between them. </p> <h3>Hierarchical</h3> <p>MIMD machines with hierarchical shared memory use a hierarchy of buses (as, for example, in a "<a href="/facts/Fat_tree/AyFyz89J">fat tree</a>") to give processors access to each other's memory. Processors on different boards may communicate through inter-nodal buses. Buses support communication between boards. With this type of architecture, the machine may support over nine thousand processors. </p> <h2 id="distributed-memory">Distributed memory</h2> <p>In distributed memory MIMD (multiple instruction, multiple data) machines, each processor has its own individual memory location. Each processor has no direct knowledge about other processor's memory. For data to be shared, it must be passed from one processor to another as a message. Since there is no shared memory, contention is not as great a problem with these machines. It is not economically feasible to connect a large number of processors directly to each other. A way to avoid this multitude of direct connections is to connect each processor to just a few others. This type of design can be inefficient because of the added time required to pass a message from one processor to another along the message path. The amount of time required for processors to perform simple message routing can be substantial. Systems were designed to reduce this time loss and <a href="/facts/Connection_Machine/wxUPNe4r">hypercube</a> and <a href="/facts/Mesh_networking/XnVSy5rK">mesh</a> are among two of the popular interconnection schemes. </p><p>Examples of distributed memory (multiple computers) include <a href="/facts/Massively_parallel_(computing)/dX7W2Nxs">MPP (massively parallel processors)</a>, <a href="/facts/Computer_cluster/mT7S1BcX">COW (clusters of workstations)</a> and NUMA (<a href="/facts/Non-uniform_memory_access/MpmN5mN0">non-uniform memory access</a>). The former is complex and expensive: Many super-computers coupled by broad-band networks. Examples include hypercube and mesh interconnections. COW is the "home-made" version for a fraction of the price.<a class="footnote-ref" id="fnref:6" href="#fn:6"><sup>6</sup></a> </p> <h3>Hypercube interconnection network</h3> <p>In an MIMD distributed memory machine with a <a href="/facts/Hypercube/q2mRPbIz">hypercube</a> system interconnection network containing four processors, a processor and a memory module are placed at each vertex of a square. The diameter of the system is the minimum number of steps it takes for one processor to send a message to the processor that is the farthest away. So, for example, the diameter of a 2-cube is 2. In a hypercube system with eight processors and each processor and memory module being placed in the vertex of a cube, the diameter is 3. In general, a system that contains 2^N processors with each processor directly connected to N other processors, the diameter of the system is N. One disadvantage of a hypercube system is that it must be configured in powers of two, so a machine must be built that could potentially have many more processors than is really needed for the application. </p> <h3>Mesh interconnection network</h3> <p>In an MIMD distributed memory machine with a mesh interconnection network, processors are placed in a two-dimensional grid. Each processor is connected to its four immediate neighbors. Wrap around connections may be provided at the edges of the mesh. One advantage of the mesh interconnection network over the hypercube is that the mesh system need not be configured in powers of two. A disadvantage is that the diameter of the mesh network is greater than the hypercube for systems with more than four processors. </p> <h2 id="see-also">See also</h2> <ul><li><a href="/facts/Symmetric_multiprocessing/T9CahUsN">SMP</a></li> <li><a href="/facts/Non-Uniform_Memory_Access/MpmN5mN0">NUMA</a></li> <li><a href="/facts/Torus_interconnect/vBDU15MN">Torus interconnect</a></li> <li><a href="/facts/Flynn%2527s_taxonomy/VrmXKDTA">Flynn's taxonomy</a></li> <li><a href="/facts/SPMD/SEDIrB0l">SPMD</a></li> <li><a href="/facts/Superscalar/gPxRAb25">Superscalar</a></li> <li><a href="/facts/Very_long_instruction_word/WJuzewyR">Very long instruction word</a></li></ul> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>"The Perils of Parallel: Larrabee vs. Nvidia, MIMD vs. SIMD". 19 September 2008. <a href="http://perilsofparallel.blogspot.gr/2008/09/larrabee-vs-nvidia-mimd-vs-simd.html" target="_blank">http://perilsofparallel.blogspot.gr/2008/09/larrabee-vs-nvidia-mimd-vs-simd.html</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>"MIMD | Intel® Developer Zone". Archived from the original on 2013-10-16. Retrieved 2013-10-16. <a href="https://web.archive.org/web/20131016215430/http://software.intel.com/en-us/articles/mimd" target="_blank">https://web.archive.org/web/20131016215430/http://software.intel.com/en-us/articles/mimd</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li> <li id="fn:3"><p>Ibaroudene, Djaffer. "Parallel Processing, EG6370G: Chapter 1, Motivation and History." Lecture Slides. St Mary's University, San Antonio, Texas. Spring 2008. <a href="/wiki/St._Mary%27s_University,_Texas" target="_blank">/wiki/St._Mary%27s_University,_Texas</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li> <li id="fn:4"><p>Ibaroudene, Djaffer. "Parallel Processing, EG6370G: Chapter 1, Motivation and History." Lecture Slides. St Mary's University, San Antonio, Texas. Spring 2008. <a href="/wiki/St._Mary%27s_University,_Texas" target="_blank">/wiki/St._Mary%27s_University,_Texas</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li> <li id="fn:5"><p>Andrew S. Tanenbaum (1997). Structured Computer Organization (4 ed.). Prentice-Hall. pp. 559–585. ISBN 978-0130959904. Archived from the original on 2013-12-01. Retrieved 2013-03-15. <a href="978-0130959904" target="_blank">978-0130959904</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></p></li> <li id="fn:6"><p>Andrew S. Tanenbaum (1997). Structured Computer Organization (4 ed.). Prentice-Hall. pp. 559–585. ISBN 978-0130959904. Archived from the original on 2013-12-01. Retrieved 2013-03-15. <a href="978-0130959904" target="_blank">978-0130959904</a> <a href="#fnref:6" class="footnote-back-ref">↩</a></p></li> </ol>