Design flow (EDA)

<h2 id="see-also">See also</h2>
<ul><li><a href="/facts/Floorplan_(microelectronics)/31eoJ3MB">Floorplan (microelectronics)</a>, creates the physical infrastructure into which the design is placed and routed</li>
<li><a href="/facts/Placement_(EDA)/lcheSkIL">Placement (EDA)</a>, an essential step in Electronic Design Automation (EDA)</li>
<li><a href="/facts/Routing_(EDA)/fMFz74oA">Routing (EDA)</a>, a crucial step in the design of integrated circuits</li>
<li><a href="/facts/Power_optimization_(EDA)/0swpw8Gc">Power optimization (EDA)</a>, the use of EDA tools to optimize (reduce) the power consumption of a digital design, while preserving its functionality</li>
<li><a href="/facts/Post-silicon_validation/8otXdtpb">Post-silicon validation</a>, the final step in the EDA design flow</li></ul>

<ul><li><i>Electronic Design Automation For Integrated Circuits Handbook</i>, by Lavagno, Martin, and Scheffer, <a href="/facts/ISBN_(identifier)/15AdSPa9">ISBN</a> 0-8493-3096-3 – A survey of the field, from which this summary was derived, with permission.</li></ul>

<h2 id="references">References</h2>

<ol>
<li id="fn:1"><p>"ASIC Design Flow in VLSI Engineering Services – A Quick Guide". 2019-06-04. Retrieved 2019-11-28. <a href="https://www.einfochips.com/blog/asic-design-flow-in-vlsi-engineering-services-a-quick-guide/" target="_blank">https://www.einfochips.com/blog/asic-design-flow-in-vlsi-engineering-services-a-quick-guide/</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li>
<li id="fn:2"><p>Basu, Joydeep (2019-10-09). "From Design to Tape-out in SCL 180 nm CMOS Integrated Circuit Fabrication Technology". IETE Journal of Education. 60 (2): 51–64. arXiv:1908.10674. doi:10.1080/09747338.2019.1657787. S2CID 201657819. <a href="/wiki/ArXiv_(identifier)" target="_blank">/wiki/ArXiv_(identifier)</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li>
</ol>

Design flow (EDA) open-in-new

Design flow (EDA)