Cache placement policies

<h2 id="direct-mapped-cache">Direct-mapped cache</h2>
<p>In a direct-mapped cache structure, the cache is organized into multiple sets<a class="footnote-ref" id="fnref:5" href="#fn:5"><sup>5</sup></a> with a single cache line per set.  Based on the address of the memory block, it can only occupy a single cache line. The cache can be framed as a  <i>n</i> × 1 column matrix.<a class="footnote-ref" id="fnref:6" href="#fn:6"><sup>6</sup></a>
</p>
<h3>To place a block in the cache</h3>
<ul><li>The set is determined by the <a href="/facts/CPU_cache/x8BYFcdv">index</a><a class="footnote-ref" id="fnref:7" href="#fn:7"><sup>7</sup></a> bits derived from the address of the memory block.</li>
<li>The memory block is placed in the set identified and the <a href="/facts/CPU_cache/x8BYFcdv">tag</a><a class="footnote-ref" id="fnref:8" href="#fn:8"><sup>8</sup></a> is stored in the tag field associated with the set.</li>
<li>If the cache line is previously occupied, then the new data replaces the memory block in the cache.</li></ul>
<h3>To search a word in the cache</h3>
<ul><li>The set is identified by the index bits of the address.</li>
<li>The tag bits derived from the memory block address are compared with the tag bits associated with the set. If the tag matches, then there is a <a href="/facts/CPU_cache/x8BYFcdv">cache hit</a> and the cache block is returned to the processor. Else there is a <a href="/facts/CPU_cache/x8BYFcdv">cache miss</a> and the memory block is fetched from the lower memory (<a href="/facts/Computer_data_storage/wPHKFpdx">main memory</a>, <a href="/facts/Computer_data_storage/wPHKFpdx">disk</a>).</li></ul>
<h3>Advantages</h3>
<ul><li>This placement policy is power efficient as it avoids the search through all the cache lines.</li>
<li>The placement policy and the <a href="/facts/CPU_cache/x8BYFcdv">replacement policy</a> is simple.</li>
<li>Simple and low-cost hardware can be used, as only one tag needs to be checked at a time.</li></ul>
<h3>Disadvantage</h3>
<ul><li>It has lower cache hit rate, as there is only one cache line available in a set. Every time a new memory is referenced to the same set, the cache line is replaced, which causes conflict miss.<a class="footnote-ref" id="fnref:9" href="#fn:9"><sup>9</sup></a></li></ul>
<h3>Example</h3>

<p>Consider a main memory of 16 kilobytes, which is organized as 4-byte blocks, and a direct-mapped cache of 256 bytes with a block size of 4 bytes. Because the main memory is 16kB, we need a minimum of 14 bits to uniquely represent a memory address. 
</p><p>Since each cache block is of size 4 bytes, the total number of sets in the cache is 256/4, which equals 64 sets.
</p><p>The incoming address to the cache is divided into bits for <a href="/facts/CPU_cache/x8BYFcdv">Offset</a>, <a href="/facts/CPU_cache/x8BYFcdv">Index</a> and <a href="/facts/CPU_cache/x8BYFcdv">Tag</a>.
</p>
<ul><li><i>Offset</i> corresponds to the bits used to determine the byte to be accessed from the cache line. Because the cache lines are 4 bytes long, there are <i>2 offset bits</i>.</li>
<li><i>Index</i> corresponds to bits used to determine the set of the Cache. There are 64 sets in the cache, and because 2^6 = 64, there are <i>6 index bits.</i></li>
<li><i>Tag</i> corresponds to the remaining bits. This means there are 14 – (6+2) = <i>6 tag bits</i>, which are stored in tag field to match the address on cache request.</li></ul>
<p>Below are memory addresses and an explanation of which cache line they map to:
</p>
<ol><li>Address 0x0000 (tag - 0b00_0000, index – 0b00_0000, offset – 0b00) corresponds to block 0 of the memory and maps to the set 0 of the cache.</li>
<li>Address 0x0004 (tag - 0b00_0000, index – 0b00_0001, offset – 0b00) corresponds to block 1 of the memory and maps to the set 1 of the cache.</li>
<li>Address 0x00FF (tag – 0b00_0000, index – 0b11_1111, offset – 0b11) corresponds to block 63 of the memory and maps to the set 63 of the cache.</li>
<li>Address 0x0100 (tag – 0b00_0001, index – 0b00_0000, offset – 0b00) corresponds to block 64 of the memory and maps to the set 0 of the cache.</li></ol>
<h2 id="fully-associative-cache">Fully associative cache</h2>
<p>In a fully associative cache, the cache is organized into a single cache set with multiple cache lines.  A memory block can occupy any of the cache lines. The cache organization can be framed as 1 × <i>m</i> row matrix.<a class="footnote-ref" id="fnref:10" href="#fn:10"><sup>10</sup></a>
</p>
<h3>To place a block in the cache</h3>
<ul><li>The cache line is selected based on the <a href="/facts/CPU_cache/x8BYFcdv">valid bit</a><a class="footnote-ref" id="fnref:11" href="#fn:11"><sup>11</sup></a> associated with it. If the valid bit is 0, the new memory block can be placed in the cache line, else it has to be placed in another cache line with valid bit 0.</li>
<li>If the cache is completely occupied then a block is evicted and the memory block is placed in that cache line.</li>
<li>The eviction of memory block from the cache is decided by the <a href="/facts/CPU_cache/x8BYFcdv">replacement policy</a>.<a class="footnote-ref" id="fnref:12" href="#fn:12"><sup>12</sup></a></li></ul>
<h3>To search a word in the cache</h3>
<ul><li>The Tag field of the memory address is compared with tag bits associated with all the cache lines. If it matches, the block is present in the cache and is a cache hit. If it does not match, then it is a cache miss and has to be fetched from the lower memory.</li>
<li>Based on the Offset, a byte is selected and returned to the processor.</li></ul>

<h3>Advantages</h3>
<ul><li>Fully associative cache structure provides us the flexibility of placing memory block in any of the cache lines and hence full utilization of the cache.</li>
<li>The placement policy provides better cache hit rate.</li>
<li>It offers the flexibility of utilizing a wide variety of <a href="/facts/CPU_cache/x8BYFcdv">replacement algorithms</a> if a cache miss occurs</li></ul>
<h3>Disadvantages</h3>
<ul><li>The placement policy is power hungry as the comparison circuitry has to run over the entire cache to locate a block.</li>
<li>The most expensive of all methods, due to the high cost of associative-comparison hardware.</li></ul>
<h3>Example</h3>
<p>Consider a main memory of 16 kilobytes, which is organized as 4-byte blocks, and a fully associative cache of 256 bytes and a block size of 4 bytes. Because the main memory is 16kB, we need a minimum of 14 bits to uniquely represent a memory address.
</p><p>The total number of sets in the cache is 1, and the set contains 256/4=64 cache lines, as the cache block is of size 4 bytes.
</p><p>The incoming address to the cache is divided into bits for offset and tag.
</p>
<ul><li><i>Offset</i> corresponds to the bits used to determine the byte to be accessed from the cache line. In the example, there are 2 offset bits, which are used to address the 4 bytes of the cache line</li>
<li><i>Tag</i> corresponds to the remaining bits. This means there are 14 – (2) = <i>12 tag bits</i>, which are stored in tag field to match the address on cache request.</li></ul>
<p>Since any block of memory can be mapped to any cache line, the memory block can occupy one of the cache lines based on the replacement policy.
</p>
<h2 id="set-associative-cache">Set-associative cache</h2>
<p>Set-associative cache is a trade-off between direct-mapped cache and fully associative cache.
</p><p>A set-associative cache can be imagined as a <i>n</i> × <i>m</i> matrix. The cache is divided into ‘n’ sets and each set contains ‘m’ cache lines. A memory block is first mapped onto a set and then placed into any cache line of the set.
</p><p>The range of caches from direct-mapped to fully associative is a continuum of levels of set associativity. (A direct-mapped cache is one-way set-associative and a fully associative cache with <i>m</i> cache lines is <i>m</i>-way set-associative.)
</p><p>Many processor caches in today's designs are either direct-mapped, two-way set-associative, or four-way set-associative.<a class="footnote-ref" id="fnref:13" href="#fn:13"><sup>13</sup></a>
</p>
<h3>To place a block in the cache</h3>
<ul><li>The set is determined by the index bits derived from the address of the memory block.</li>
<li>The memory block is placed in an available cache line in the set identified, and the tag is stored in the tag field associated with the line. If all the cache lines in the set are occupied, then the new data replaces the block identified through the <a href="/facts/CPU_cache/x8BYFcdv">replacement policy</a>.</li></ul>
<h3>To locate a word in the cache</h3>
<ul><li>The set is determined by the index bits derived from the address of the memory block.</li>
<li>The tag bits are compared with the tags of all cache lines present in selected set. If the tag matches any of the cache lines, it is a cache hit and the appropriate line is returned. If the tag does not match any of the lines, then it is a cache miss and the data is requested from next level in the memory hierarchy.</li></ul>
<h3>Advantages</h3>
<ul><li>The placement policy is a trade-off between direct-mapped and fully associative cache.</li>
<li>It offers the flexibility of using <a href="/facts/CPU_cache/x8BYFcdv">replacement algorithms</a> if a cache miss occurs.</li></ul>
<h3>Disadvantages</h3>
<ul><li>The placement policy will not effectively use all the available cache lines in the cache and suffers from <a href="/facts/Cache_performance_measurement_and_metric/Gby4IQ8a">conflict miss</a>.</li></ul>
<h3>Example</h3>
<p>Consider a main memory of 16 kilobytes, which is organized as 4-byte blocks, and a 2-way set-associative cache of 256 bytes with a block size of 4 bytes. Because the main memory is 16kB, we need a minimum of 14 bits to uniquely represent a memory address.
</p><p>Since each cache block is of size 4 bytes and is 2-way set-associative, the total number of sets in the cache is 256/(4 * 2), which equals 32 sets.
</p>

<p>The incoming address to the cache is divided into bits for Offset, Index and Tag.
</p>
<ul><li><i>Offset</i> corresponds to the bits used to determine the byte to be accessed from the cache line. Because the cache lines are 4 bytes long, there are <i>2 offset bits</i>.</li>
<li><i>Index</i> corresponds to bits used to determine the set of the Cache. There are 32 sets in the cache, and because 2^5 = 32, there are <i>5 index bits.</i></li>
<li><i>Tag</i> corresponds to the remaining bits. This means there are 14 – (5+2) = <i>7 bits</i>, which are stored in tag field to match the address on cache request.</li></ul>
<p>Below are memory addresses and an explanation of which cache line on which set they map to:
</p>
<ol><li>Address 0x0000 (tag - 0b000_0000, index – 0b0_0000, offset – 0b00) corresponds to block 0 of the memory and maps to the set 0 of the cache. The block occupies a cache line in set 0, determined by the replacement policy for the cache.</li>
<li>Address 0x0004 (tag - 0b000_0000, index – 0b0_0001, offset – 0b00) corresponds to block 1 of the memory and maps to the set 1 of the cache. The block occupies a cache line in set 1, determined by the replacement policy for the cache.</li>
<li>Address 0x00FF (tag – 0b000_0001, index – 0b1_1111, offset – 0b11) corresponds to block 63 of the memory and maps to the set 31 of the cache. The block occupies a cache line in set 31, determined by the replacement policy for the cache.</li>
<li>Address 0x0100 (tag – 0b000_0010, index – 0b0_0000, offset – 0b00) corresponds to block 64 of the memory and maps to the set 0 of the cache. The block occupies a cache line in set 0, determined by the replacement policy for the cache.</li></ol>
<h2 id="two-way-skewed-associative-cache">Two-way skewed associative cache</h2>
<p>Other schemes have been suggested, such as the <i>skewed cache</i>,<a class="footnote-ref" id="fnref:14" href="#fn:14"><sup>14</sup></a> where the index for way 0 is direct, as above, but the index for way 1 is formed with a <a href="/facts/Hash_function/rk6MlCt3">hash function</a>. A good hash function has the property that addresses which conflict with the direct mapping tend not to conflict when mapped with the hash function, and so it is less likely that a program will suffer from an unexpectedly large number of conflict misses due to a pathological access pattern. The downside is extra latency from computing the hash function.<a class="footnote-ref" id="fnref:15" href="#fn:15"><sup>15</sup></a> Additionally, when it comes time to load a new line and evict an old line, it may be difficult to determine which existing line was least recently used, because the new line conflicts with data at different indexes in each way; <a href="/facts/Cache_algorithms/LFW5UqPo">LRU</a> tracking for non-skewed caches is usually done on a per-set basis. Nevertheless, skewed-associative caches have major advantages over conventional set-associative ones.<a class="footnote-ref" id="fnref:16" href="#fn:16"><sup>16</sup></a>
</p>
<h2 id="pseudo-associative-cache">Pseudo-associative cache</h2>
<p>A true set-associative cache tests all the possible ways simultaneously, using something like a <a href="/facts/Content-addressable_memory/VteSPHMR">content-addressable memory</a>. A pseudo-associative cache tests each possible way one at a time. A hash-rehash cache and a column-associative cache are examples of a pseudo-associative cache.
</p><p>In the common case of finding a hit in the first way tested, a pseudo-associative cache is as fast as a direct-mapped cache, but it has a much lower conflict miss rate than a direct-mapped cache, closer to the miss rate of a fully associative cache.<a class="footnote-ref" id="fnref:17" href="#fn:17"><sup>17</sup></a>
</p>
<h2 id="see-also">See also</h2>
<ul><li><a href="/facts/CPU_cache/x8BYFcdv">Associativity</a></li>
<li><a href="/facts/Cache_algorithms/LFW5UqPo">Cache replacement policy</a></li>
<li><a href="/facts/Cache_hierarchy/9lGPQ5r6">Cache hierarchy</a></li>
<li><a href="/facts/Cache_(computing)/gmJYN8wm">Writing Policies</a></li>
<li><a href="/facts/Cache_coloring/68NjspRE">Cache coloring</a></li></ul>

<h2 id="references">References</h2>

<ol>
<li id="fn:1"><p>"The Basics of Cache" (PDF). <a href="https://cseweb.ucsd.edu/classes/su07/cse141/cache-handout.pdf" target="_blank">https://cseweb.ucsd.edu/classes/su07/cse141/cache-handout.pdf</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li>
<li id="fn:2"><p>"Cache Placement Policies". Archived from the original on Feb 21, 2020. <a href="https://web.archive.org/web/20200221213947/http://web.cs.iastate.edu/~prabhu/Tutorial/CACHE/bl_place.html" target="_blank">https://web.archive.org/web/20200221213947/http://web.cs.iastate.edu/~prabhu/Tutorial/CACHE/bl_place.html</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li>
<li id="fn:3"><p>"Placement Policies". Archived from the original on August 14, 2020. <a href="https://web.archive.org/web/20200814000302/http://fourier.eng.hmc.edu/e85_old/lectures/memory/node4.html" target="_blank">https://web.archive.org/web/20200814000302/http://fourier.eng.hmc.edu/e85_old/lectures/memory/node4.html</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li>
<li id="fn:4"><p>Mattson, R.L.; Gecsei, J.; Slutz, D. R.; Traiger, I (1970). "Evaluation Techniques for Storage Hierarchies". IBM Systems Journal. 9 (2): 78–117. doi:10.1147/sj.92.0078. <a href="/wiki/Richard_Mattson" target="_blank">/wiki/Richard_Mattson</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li>
<li id="fn:5"><p>"The Basics of Cache" (PDF). <a href="https://cseweb.ucsd.edu/classes/su07/cse141/cache-handout.pdf" target="_blank">https://cseweb.ucsd.edu/classes/su07/cse141/cache-handout.pdf</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></p></li>
<li id="fn:6"><p>Solihin, Yan (2015). Fundamentals of Parallel Multi-core Architecture. Taylor & Francis. pp. 136–141. ISBN 978-1482211184. <a href="978-1482211184" target="_blank">978-1482211184</a> <a href="#fnref:6" class="footnote-back-ref">↩</a></p></li>
<li id="fn:7"><p>"The Basics of Cache" (PDF). <a href="https://cseweb.ucsd.edu/classes/su07/cse141/cache-handout.pdf" target="_blank">https://cseweb.ucsd.edu/classes/su07/cse141/cache-handout.pdf</a> <a href="#fnref:7" class="footnote-back-ref">↩</a></p></li>
<li id="fn:8"><p>"The Basics of Cache" (PDF). <a href="https://cseweb.ucsd.edu/classes/su07/cse141/cache-handout.pdf" target="_blank">https://cseweb.ucsd.edu/classes/su07/cse141/cache-handout.pdf</a> <a href="#fnref:8" class="footnote-back-ref">↩</a></p></li>
<li id="fn:9"><p>"Cache Miss Types" (PDF). <a href="http://meseec.ce.rit.edu/eecc551-winter2001/551-1-30-2002.pdf" target="_blank">http://meseec.ce.rit.edu/eecc551-winter2001/551-1-30-2002.pdf</a> <a href="#fnref:9" class="footnote-back-ref">↩</a></p></li>
<li id="fn:10"><p>Solihin, Yan (2015). Fundamentals of Parallel Multi-core Architecture. Taylor & Francis. pp. 136–141. ISBN 978-1482211184. <a href="978-1482211184" target="_blank">978-1482211184</a> <a href="#fnref:10" class="footnote-back-ref">↩</a></p></li>
<li id="fn:11"><p>"The Basics of Cache" (PDF). <a href="https://cseweb.ucsd.edu/classes/su07/cse141/cache-handout.pdf" target="_blank">https://cseweb.ucsd.edu/classes/su07/cse141/cache-handout.pdf</a> <a href="#fnref:11" class="footnote-back-ref">↩</a></p></li>
<li id="fn:12"><p>"Fully Associative Cache". Archived from the original on December 24, 2017. <a href="https://web.archive.org/web/20171224054857/http://www.cs.umd.edu/class/sum2003/cmsc311/Notes/Memory/fully.html" target="_blank">https://web.archive.org/web/20171224054857/http://www.cs.umd.edu/class/sum2003/cmsc311/Notes/Memory/fully.html</a> <a href="#fnref:12" class="footnote-back-ref">↩</a></p></li>
<li id="fn:13"><p>Solihin, Yan (2015). Fundamentals of Parallel Multi-core Architecture. Taylor & Francis. pp. 136–141. ISBN 978-1482211184. <a href="978-1482211184" target="_blank">978-1482211184</a> <a href="#fnref:13" class="footnote-back-ref">↩</a></p></li>
<li id="fn:14"><p>André Seznec (1993). "A Case for Two-Way Skewed-Associative Caches". ACM SIGARCH Computer Architecture News. 21 (2): 169–178. doi:10.1145/173682.165152. <a href="/wiki/Andr%C3%A9_Seznec" target="_blank">/wiki/Andr%C3%A9_Seznec</a> <a href="#fnref:14" class="footnote-back-ref">↩</a></p></li>
<li id="fn:15"><p>C. Kozyrakis. "Lecture 3: Advanced Caching Techniques" (PDF). Archived from the original (PDF) on September 7, 2012. <a href="/wiki/Christos_Kozyrakis" target="_blank">/wiki/Christos_Kozyrakis</a> <a href="#fnref:15" class="footnote-back-ref">↩</a></p></li>
<li id="fn:16"><p>Micro-Architecture "Skewed-associative caches have ... major advantages over conventional set-associative caches." <a href="http://www.irisa.fr/caps/PROJECTS/Architecture/" target="_blank">http://www.irisa.fr/caps/PROJECTS/Architecture/</a> <a href="#fnref:16" class="footnote-back-ref">↩</a></p></li>
<li id="fn:17"><p>C. Kozyrakis. "Lecture 3: Advanced Caching Techniques" (PDF). Archived from the original (PDF) on September 7, 2012. <a href="/wiki/Christos_Kozyrakis" target="_blank">/wiki/Christos_Kozyrakis</a> <a href="#fnref:17" class="footnote-back-ref">↩</a></p></li>
</ol>

Cache placement policies open-in-new

Cache placement policies