However, the instructions/cycle measurement depends on the instruction sequence, the data and external factors.
Before standard benchmarks were available, average speed rating of computers was based on calculations for a mix of instructions with the results given in kilo instructions per second (kIPS). The most famous was the Gibson Mix, produced by Jack Clark Gibson of IBM for scientific applications in 1959.
Other ratings, such as the ADP mix which does not include floating point operations, were produced for commercial applications. The thousand instructions per second (kIPS) unit is rarely used today, as most current microprocessors can execute at least a million instructions per second.
The speed of a given CPU depends on many factors, such as the type of instructions being executed, the execution order and the presence of branch instructions (problematic in CPU pipelines). CPU instruction rates are different from clock frequencies, usually reported in Hz, as each instruction may require several clock cycles to complete or the processor may be capable of executing multiple independent instructions simultaneously. MIPS can be useful when comparing performance between processors made with similar architecture (e.g. Microchip branded microcontrollers), but they are difficult to compare between differing CPU architectures. This led to the term "Meaningless Indicator of Processor Speed," or less commonly, "Meaningless Indices of Performance," being popular amongst technical people by the mid-1980s.
For this reason, MIPS has become not a measure of instruction execution speed, but task performance speed compared to a reference. In the late 1970s, minicomputer performance was compared using VAX MIPS, where computers were measured on a task and their performance rated against the VAX-11/780 that was marketed as a 1 MIPS machine. (The measure was also known as the VAX Unit of Performance or VUP.) This was chosen because the 11/780 was roughly equivalent in performance to an IBM System/370 model 158–3, which was commonly accepted in the computing industry as running at 1 MIPS.
Effective MIPS speeds are highly dependent on the programming language used. The Whetstone Report has a table showing MWIPS speeds of PCs via early interpreters and compilers up to modern languages. The first PC compiler was for BASIC (1982) when a 4.8 MHz 8088/87 CPU obtained 0.01 MWIPS. Results on a 2.4 GHz Intel Core 2 Duo (1 CPU 2007) vary from 9.7 MWIPS using BASIC Interpreter, 59 MWIPS via BASIC Compiler, 347 MWIPS using 1987 Fortran, 1,534 MWIPS through HTML/Java to 2,403 MWIPS using a modern C/C++ compiler.
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LINKS-1 Computer Graphics System: 257× Zilog Z8001 [7] Archived 7 May 2017 at the Wayback Machine at 10 MHz [8] Archived 6 October 2014 at the Wayback Machine (2.5 MIPS [9] Archived 2015-06-09 at the Wayback Machine) each http://museum.ipsj.or.jp/en/computer/other/0013.html
Sega System 16: Hitachi-Motorola 68000 @ 10 MHz (1.75 MIPS), NEC-Zilog Z80 @ 4 MHz (0.58 MIPS) [10] Archived 21 April 2016 at the Wayback Machine [11] Archived 9 March 2020 at the Wayback Machine, Intel 8751 @ 8 MHz [12] (8 MIPS [13] Archived 26 August 2016 at the Wayback Machine), Intel 8048 @ 6 MHz "Sega Pre-System 16 hardware notes". Archived from the original on 25 January 2016. Retrieved 8 August 2016. (6 MIPS [14]) http://www.system16.com/hardware.php?id=695
Namco System 21 hardware: 5× Texas Instruments TMS320C20 @ 25 MHz (62.5 MIPS [15] Archived 1 October 2014 at the Wayback Machine), 2× Motorola 68000 @ 12.288 MHz [16] Archived 18 May 2015 at the Wayback Machine (4.301 MIPS [17] Archived 9 March 2020 at the Wayback Machine), Motorola 68020 [18] @ 12.5 MHz (3.788 MIPS [19] Archived 1 November 2012 at the Wayback Machine), Hitachi HD63705 @ 2.048 MHz [20] (2.048 MIPS [21]), Motorola 6809 @ 3.072 MHz [22] (1.29 MIPS [23] ) http://historyofracinggames.files.wordpress.com/2007/06/060-1987-drivers-eyes-1989-winning-run.pdf
Atari Hard Drivin' hardware: [24] Archived 29 September 2014 at the Wayback Machine Motorola 68000 @ 7 MHz (1.225 MIPS [25] Archived 9 March 2020 at the Wayback Machine), Motorola 68010 @ 7 MHz (1.348 MIPS [26] Archived 6 October 2014 at the Wayback Machine), 3× Texas Instruments TMS34010 @ 50 MHz (18 MIPS [27]), Analog Devices ADSP-2100 @ 8 MHz (8 MIPS [28]), Texas Instruments TMS32010 @ 20 MHz (5 MIPS "TMS320C1x Digital Signal Processors" (PDF). Archived from the original (PDF) on 6 October 2014. Retrieved 17 September 2014.) http://www.system16.com/hardware.php?id=770
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Namco System 21 (Galaxian³) hardware: [29] 80× Texas Instruments TMS320C25 @ 40 MHz (1600 MIPS [30] Archived 1 October 2014 at the Wayback Machine), 5× Motorola 68020 @ 24.576 MHz (37.236 MIPS [31] Archived 1 November 2012 at the Wayback Machine) Motorola 68000 @ 12.288 MHz (2.15 MIPS [32] Archived 9 March 2020 at the Wayback Machine), 10× Motorola 68000 @ 12 MHz (21 MIPS [33] ) https://archive.today/20141121115053/https://github.com/mamedev/mame/tree/master/src/mame/drivers/gal3.c
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Sega Naomi Multiboard hardware: [35] Archived 3 March 2016 at the Wayback Machine [36] Archived 2014-10-06 at the Wayback Machine 16× Hitachi SH-4 at 200 MHz (5760 MIPS [37] Archived 2014-12-11 at the Wayback Machine), 16× ARM7 at 45 MHz (640 MIPS [38]) http://www.system16.com/hardware.php?id=906
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