Menu
Home
People
Places
Arts
History
Plants & Animals
Science
Life & Culture
Technology
Reference.org
Memory-mapped I/O and port-mapped I/O
open-in-new
<h2 id="overview">Overview</h2> <p>Different CPU-to-device communication methods, such as memory mapping, do not affect the <a href="/facts/Direct_memory_access/DWuVgclV">direct memory access</a> (DMA) for a device, because, by definition, DMA is a memory-to-device communication method that bypasses the CPU. </p><p>Hardware <a href="/facts/Interrupt/Mm6C4rpc">interrupts</a> are another communication method between the CPU and peripheral devices, however, for a number of reasons, interrupts are always treated separately. An interrupt is device-initiated, as opposed to the methods mentioned above, which are CPU-initiated. It is also unidirectional, as information flows only from device to CPU. Lastly, each interrupt line carries only one <a href="/facts/Bit/S972NSaD">bit</a> of information with a fixed meaning, namely "an event that requires attention has occurred in a device on this interrupt line". </p><p>I/O operations can slow memory access if the address and data buses are shared. This is because the peripheral device is usually much slower than main memory. In some architectures, port-mapped I/O operates via a dedicated I/O bus, alleviating the problem. </p><p>One merit of memory-mapped I/O is that, by discarding the extra complexity that port I/O brings, a CPU requires less internal logic and is thus cheaper, faster, easier to build, consumes less power and can be physically smaller; this follows the basic tenets of <a href="/facts/RISC/aQbGM62p">reduced instruction set computing</a>, and is also advantageous in <a href="/facts/Embedded_system/a4muX1wU">embedded systems</a>. The other advantage is that, because regular memory instructions are used to address devices, all of the CPU's addressing modes are available for the I/O as well as the memory, and instructions that perform an <a href="/facts/Arithmetic_logic_unit/SgIjPzSc">ALU</a> operation directly on a memory operand (loading an operand from a memory location, storing the result to a memory location, or both) can be used with I/O device registers as well. In contrast, port-mapped I/O instructions are often very limited, often providing only for simple load-and-store operations between CPU registers and I/O ports, so that, for example, to add a constant to a port-mapped device register would require three instructions: read the port to a CPU register, add the constant to the CPU register, and write the result back to the port. </p><p>As <a href="/facts/16-bit/bTGS44Ne">16-bit</a> processors have become obsolete and replaced with <a href="/facts/32-bit/TDMVce8s">32-bit</a> and <a href="/facts/64-bit/AgvkQHkM">64-bit</a> in general use, reserving ranges of memory address space for I/O is less of a problem, as the memory address space of the processor is usually much larger than the required space for all memory and I/O devices in a system. Therefore, it has become more frequently practical to take advantage of the benefits of memory-mapped I/O. However, even with address space being no longer a major concern, neither I/O mapping method is universally superior to the other, and there will be cases where using port-mapped I/O is still preferable. </p> <h3>x86</h3> <p>Memory-mapped I/O is preferred in <a href="/facts/IA-32/7yTv1aHH">IA-32</a> and <a href="/facts/X86-64/cyWvUFlP">x86-64</a> based architectures because the instructions that perform port-based I/O are limited to one register: EAX, AX, and AL are the only registers that data can be moved into or out of, and either a byte-sized immediate value in the instruction or a value in register DX determines which port is the source or destination port of the transfer.<a class="footnote-ref" id="fnref:5" href="#fn:5"><sup>5</sup></a><a class="footnote-ref" id="fnref:6" href="#fn:6"><sup>6</sup></a> Since any general-purpose register can send or receive data to or from memory and memory-mapped I/O devices, memory-mapped I/O uses fewer instructions and can run faster than port I/O. <a href="/facts/AMD/CB1G7QTb">AMD</a> did not extend the port I/O instructions when defining the <a href="/facts/X86-64/cyWvUFlP">x86-64</a> architecture to support 64-bit ports, so 64-bit transfers cannot be performed using port I/O.<a class="footnote-ref" id="fnref:7" href="#fn:7"><sup>7</sup></a> </p><p>On newer Intel platforms beginning with 2008 <a href="/facts/Intel_5_Series/xfxWI5Tt">5 series</a>, I/O devices on the chipset directly communicate via a dedicated <a href="/facts/Direct_Media_Interface/ylK0cfmm">Direct Media Interface</a> (DMI) bus.<a class="footnote-ref" id="fnref:8" href="#fn:8"><sup>8</sup></a><a class="footnote-ref" id="fnref:9" href="#fn:9"><sup>9</sup></a> </p> <h2 id="memory-barriers">Memory barriers</h2> <p>Since the <a href="/facts/Cache_(computing)/gmJYN8wm">caches</a> mediate accesses to memory addresses, data written to different addresses may reach the peripherals' memory or registers out of the program order, i.e. if software writes data to an address and then writes data to another address, the cache <a href="/facts/Write_buffer/cCBz8DqA">write buffer</a> does not guarantee that the data will reach the peripherals in that order.<a class="footnote-ref" id="fnref:10" href="#fn:10"><sup>10</sup></a> Any program that does not include <a href="/facts/Memory_barrier/am65f6bs">cache-flushing</a> instructions after each write in the sequence may see unintended IO effects if a cache system optimizes the write order. Writes to memory can often be reordered to reduce redundancy or to make better use of memory access cycles without changing the final state of what got stored; whereas, the same optimizations might completely change the meaning and effect of writes to memory-mapped I/O regions. </p><p>Lack of foresight in the choice of memory-mapped I/O regions led to many of the RAM-capacity barriers in older generations of computers. Designers rarely expected machines to grow to make full use of an architecture's theoretical RAM capacity, and thus often used some of the high-order bits of the address-space as selectors for memory-mapped I/O functions. For example, the <a href="/facts/640_KB_barrier/hLcfWzlB">640 KB barrier</a> in the IBM PC and derivatives is due to reserving the region between 640 and 1024 KB (64k segments 10 through 16) for the <a href="/facts/Upper_Memory_Area/CLE38IvM">Upper Memory Area</a>. This choice initially made little impact, but it eventually limited the total amount of RAM available within the 20-bit available address space. The <a href="/facts/3_GB_barrier/fRQwMtFP">3 GB barrier</a> and <a href="/facts/PCI_hole/1xPyujgB">PCI hole</a> are similar manifestations of this with 32-bit address spaces, exacerbated by details of the <a href="/facts/X86/Kypq5fgu">x86</a> boot process and <a href="/facts/Memory_management_unit/tJQtAQzI">MMU</a> design. 64-bit architectures often technically have similar issues, but these only rarely have practical consequences. </p> <h2 id="examples">Examples</h2> A sample system memory map<table><tbody><tr><th>Address range (<a href="/facts/Hexadecimal/02ohQW22">hexadecimal</a>)</th><th>Size</th><th>Device</th></tr><tr><th>0000–7FFF</th><td>32 KiB</td><td>RAM</td></tr><tr><th>8000–80FF</th><td>256 bytes</td><td>General-purpose I/O</td></tr><tr><th>9000–90FF</th><td>256 bytes</td><td>Sound controller</td></tr><tr><th>A000–A7FF</th><td>2 KiB</td><td>Video controller/text-mapped display RAM</td></tr><tr><th>C000–FFFF</th><td>16 KiB</td><td>ROM</td></tr></tbody></table> <p>A simple system built around an <a href="/facts/8-bit/2CkhLNoH">8-bit</a> <a href="/facts/Microprocessor/Fx9CaQht">microprocessor</a> might provide 16-bit address lines, allowing it to address up to 64 <a href="/facts/Kibibyte/BNHUp9Qq">kibibytes</a> (KiB) of memory. On such a system, the first 32 KiB of address space may be allotted to <a href="/facts/Random_access_memory/DuD4bxh6">random access memory</a> (RAM), another 16 KiB to <a href="/facts/Read-only_memory/P9QMuDLH">read-only memory</a> (ROM) and the remainder to a variety of other devices such as timers, counters, video display chips, sound generating devices, etc. </p><p>The hardware of the system is arranged so that devices on the address bus will only respond to particular addresses which are intended for them, while all other addresses are ignored. This is the job of the <a href="/facts/Address_decoder/VHp8fxNI">address decoding circuitry</a>, and that establishes the <a href="/facts/Memory_map/XoaWKv3e">memory map</a> of the system. As a result, system's memory map may look like in the table on the right. This memory map contains gaps, which is also quite common in actual system architectures. </p><p>Assuming the fourth register of the video controller sets the background colour of the screen, the CPU can set this colour by writing a value to the memory location A003 using its standard memory write instruction. Using the same method, graphs can be displayed on a screen by writing character values into a special area of RAM within the video controller. Prior to cheap <a href="/facts/Random_access_memory/DuD4bxh6">RAM</a> that enabled <a href="/facts/Bitmap/Fr80ySnT">bit-mapped displays</a>, this character cell method was a popular technique for computer video displays (see <a href="/facts/Text_user_interface/bngNtqIY">Text user interface</a>). </p> <h2 id="basic-types-of-address-decoding">Basic types of address decoding</h2> <p>Address decoding types, in which a device may decode addresses completely or incompletely, include the following: </p> Complete (exhaustive) decoding 1:1 mapping of unique addresses to one hardware register (physical memory location). Involves checking every line of the <a href="/facts/Address_bus/R45TKwS7">address bus</a>. Incomplete (partial) decoding <i>n</i>:1 mapping of n unique addresses to one hardware register. Partial decoding allows a memory location to have more than one address, allowing the programmer to reference a memory location using n different addresses. It may also be done to simplify the decoding hardware by using simpler and often cheaper logic that examines only some address lines, when not all of the CPU's address space is needed. Commonly, the decoding itself is programmable, so the system can reconfigure its own memory map as required, though this is a newer development and generally in conflict with the intent of being cheaper. Synonyms: foldback, multiply mapped, partially mapped, address <a href="/facts/Aliasing_(computing)/C7wT3dQy">aliasing</a>.<a class="footnote-ref" id="fnref:11" href="#fn:11"><sup>11</sup></a><a class="footnote-ref" id="fnref:12" href="#fn:12"><sup>12</sup></a> Linear decoding Address lines are used directly without any decoding logic. This is done with devices such as RAMs and ROMs that have a sequence of address inputs, and with peripheral chips that have a similar sequence of inputs for addressing a bank of registers. Linear addressing is rarely used alone (only when there are few devices on the bus, as using purely linear addressing for more than one device usually wastes a lot of address space) but instead is combined with one of the other methods to select a device or group of devices within which the linear addressing selects a single register or memory location. <h2 id="port-io-via-device-drivers">Port I/O via device drivers</h2> <p>In Windows-based computers, memory can also be accessed via specific drivers such as DOLLx8KD which gives I/O access in 8-, 16- and 32-bit on most Windows platforms starting from Windows 95 up to Windows 7. Installing I/O port drivers will ensure memory access by activating the drivers with simple DLL calls allowing port I/O and when not needed, the driver can be closed to prevent unauthorized access to the I/O ports. </p><p>Linux provides the pcimem utility to allow reading from and writing to MMIO addresses. The Linux kernel also allows tracing MMIO access from kernel modules (drivers) using the kernel's <i>mmiotrace</i> debug facility. To enable this, the Linux kernel should be compiled with the corresponding option enabled. <i>mmiotrace</i> is used for debugging closed-source device drivers. </p> <h2 id="see-also">See also</h2> <ul><li><a href="/facts/Programmed_input%25E2%2580%2593output/oKGcQrkI">Programmed input–output</a></li> <li><a href="/facts/Mmap/QCtfjG5u">mmap</a>, not to be confused with memory-mapped I/O</li> <li><a href="/facts/Memory-mapped_file/veYrNQnl">Memory-mapped file</a></li> <li>Early examples of computers with port-mapped I/O <ul><li><a href="/facts/PDP-8/udvrynE8">PDP-8</a></li> <li><a href="/facts/Data_General_Nova/z4YhpLuD">Nova</a></li></ul></li> <li><a href="/facts/PDP-11/9HkGUzFn">PDP-11</a>, an early example of a computer architecture using memory-mapped I/O <ul><li><a href="/facts/Unibus/HGEzSfuY">Unibus</a>, a memory and I/O bus used by the PDP-11</li></ul></li> <li><a href="/facts/Bank_switching/9y09qE2k">Bank switching</a></li> <li><a href="/facts/Ralf_Brown%2527s_Interrupt_List/dzYVSXxV">Ralf Brown's Interrupt List</a></li> <li><a href="/facts/Coprocessor/WsVXzAGo">Coprocessor</a></li> <li><a href="/facts/Direct_memory_access/DWuVgclV">Direct memory access</a></li> <li><a href="/facts/Advanced_Configuration_and_Power_Interface/GnLLzfyr">Advanced Configuration and Power Interface</a> (ACPI)</li> <li><a href="/facts/Speculative_execution_CPU_vulnerabilities/GVJuTcCM">Speculative execution CPU vulnerabilities</a></li></ul> <h2 id="notes">Notes</h2> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>A memory that besides registers is directly accessible by the processor, e.g. DRAM in IBM PC compatible computers or Flash/SRAM in microcontrollers. <a href="/wiki/DRAM" target="_blank">/wiki/DRAM</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>Hayes, John P. (1978). Computer Architecture and Organization. McGraw-Hill International Book Company. p. 419. ISBN 0-07-027363-4. <a href="0-07-027363-4" target="_blank">0-07-027363-4</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li> <li id="fn:3"><p>Dandamudi, Sivarama P. (2006-05-31). "Chapter 19 Input/Output Organization" (PDF). Fundamentals of Computer Organization and Design. Springer Science+Business Media. ISBN 978-0-387-21566-2. <a href="978-0-387-21566-2" target="_blank">978-0-387-21566-2</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li> <li id="fn:4"><p>"Bochs VBE Extensions - OSDev Wiki". <a href="https://wiki.osdev.org/Bochs_VBE_Extensions" target="_blank">https://wiki.osdev.org/Bochs_VBE_Extensions</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li> <li id="fn:5"><p>"Intel 64 and IA-32 Architectures Software Developer's Manual: Volume 2A: Instruction Set Reference, A-M" (PDF). Intel 64 and IA-32 Architectures Software Developer's Manual. Intel Corporation. June 2010. pp. 3–520. Retrieved 2010-08-21. <a href="http://www.intel.com/Assets/PDF/manual/253666.pdf" target="_blank">http://www.intel.com/Assets/PDF/manual/253666.pdf</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></p></li> <li id="fn:6"><p>"Intel 64 and IA-32 Architectures Software Developer's Manual: Volume 2B: Instruction Set Reference, N-Z" (PDF). Intel 64 and IA-32 Architectures Software Developer's Manual. Intel Corporation. June 2010. pp. 4–22. Retrieved 2010-08-21. <a href="http://www.intel.com/Assets/PDF/manual/253667.pdf" target="_blank">http://www.intel.com/Assets/PDF/manual/253667.pdf</a> <a href="#fnref:6" class="footnote-back-ref">↩</a></p></li> <li id="fn:7"><p>"AMD64 Architecture Programmer's Manual: Volume 3: General-Purpose and System Instructions" (PDF). AMD64 Architecture Programmer's Manual. Advanced Micro Devices. November 2009. pp. 117, 181. Retrieved 2010-08-21. <a href="https://www.amd.com/system/files/TechDocs/24594.pdf" target="_blank">https://www.amd.com/system/files/TechDocs/24594.pdf</a> <a href="#fnref:7" class="footnote-back-ref">↩</a></p></li> <li id="fn:8"><p>See Intel datasheets on specific CPU family e.g. 2014 "10th Generation Intel Processor Families" (PDF). Intel. April 2020. Retrieved 2023-06-05.; <a href="https://www.intel.com.tw/content/dam/www/public/us/en/documents/datasheets/10th-gen-core-families-datasheet-vol-2-datasheet.pdf" target="_blank">https://www.intel.com.tw/content/dam/www/public/us/en/documents/datasheets/10th-gen-core-families-datasheet-vol-2-datasheet.pdf</a> <a href="#fnref:8" class="footnote-back-ref">↩</a></p></li> <li id="fn:9"><p>"What Is the Direct Media Interface (DMI) of Intel Processors?". Intel. Retrieved 2023-06-05. <a href="https://www.intel.com/content/www/in/en/support/articles/000094185/processors.html" target="_blank">https://www.intel.com/content/www/in/en/support/articles/000094185/processors.html</a> <a href="#fnref:9" class="footnote-back-ref">↩</a></p></li> <li id="fn:10"><p>ARM Cortex-A Series Programmer's Guide. Literature number ARM DEN0013D. pp. 10–13. <a href="#fnref:10" class="footnote-back-ref">↩</a></p></li> <li id="fn:11"><p>"Partial Address Decoding and I/O Space in Windows Operating Systems". Microsoft. 2001-12-04. <a href="http://www.microsoft.com/whdc/system/sysinternals/partialaddress.mspx#EFD" target="_blank">http://www.microsoft.com/whdc/system/sysinternals/partialaddress.mspx#EFD</a> <a href="#fnref:11" class="footnote-back-ref">↩</a></p></li> <li id="fn:12"><p>"Address aliasing". Hewlett-Packard. <a href="http://docs.hp.com/en/A3725-96022/ch03s03.html" target="_blank">http://docs.hp.com/en/A3725-96022/ch03s03.html</a> <a href="#fnref:12" class="footnote-back-ref">↩</a></p></li> </ol>