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Intel Tera-Scale
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<h2 id="prototypes">Prototypes</h2> <p><a href="/facts/Teraflops_Research_Chip/fp2yVaKM">Teraflops Research Chip</a> (Polaris) is an 80-core prototype processor developed by Intel in 2007. It represents Intel's first public attempt at creating a Tera-Scale processor. The Polaris processor requires to be run at 3.13 GHz and 1V in order to maintain its teraFLOP name. At its peak performance, the processor is capable of 1.28 teraFLOP.<a class="footnote-ref" id="fnref:2" href="#fn:2"><sup>2</sup></a> </p><p><a href="/facts/Single-chip_Cloud_Computer/D1gCDhG3">Single-chip Cloud Computer</a> is another research processor developed by Intel in 2009. This processor consists of 48 P54C cores connected in a 6x4 2D-mesh.<a class="footnote-ref" id="fnref:3" href="#fn:3"><sup>3</sup></a> </p> <h2 id="ideology">Ideology</h2> <p>Parallelism is the concept of performing multiple tasks simultaneously, effectively reducing the time needed to perform a given task. The Tera-Scale research program is focused on the concept of utilizing many more cores than conventional to increase performance with parallelism. Based on their previous experience with increased core counts on CPUs, doubling the number of cores was able to nearly double the performance with no increase in power. With a greater amount of cores, there are possibilities of improved energy efficiency, improved performance, extended lifetimes and new capabilities. Tera-Scale processors would improve energy efficiency by being able to "put to sleep" cores that are unneeded at the time while being able to improve performance by intelligently redistributing workloads to ensure an even workload spread across the chip. Extended lifetimes are also capable by tera-scale processors due to the possibility of having reserve cores that could be brought online when a core fails in the processor. Lastly, the processors would gain new capabilities and functionality as dedicated hardware engines, such as graphics engines, could be integrated.<a class="footnote-ref" id="fnref:4" href="#fn:4"><sup>4</sup></a> </p> <h2 id="hardware">Hardware</h2> <p>Intel Tera-Scale is focused on creating multi-core processors that can utilize parallel processing to reach teraFLOPS of computing performance. Current processors consist of highly complicated cores; however, current cores are built in a way that makes it difficult to have more than the current amounts of cores in CPUs. As a result, Intel is currently focused on creating Tera-Scale processors with many cores rather than high performance cores. To simplify CPU cores, Intel moved from CPUs utilizing the <a href="/facts/X86/Kypq5fgu">x86</a> architecture to a much simpler <a href="/facts/Very_long_instruction_word/WJuzewyR">VLIW</a> architecture. VLIW is an uncommon architecture for desktops, but is adequate for computers running specialized applications. This architecture simplifies hardware design at the cost of the increasing the workload on the compiler side meaning more work must be put into programming. This drawback is offset by the fact that the number of applications that will be run on a Tera-Scale processor is low enough for it to not be too much of a burden on the software side.<a class="footnote-ref" id="fnref:5" href="#fn:5"><sup>5</sup></a> </p> <h2 id="software">Software</h2> <p>With the release of the Polaris 80 core processor in 2007, people questioned the need of tens or hundreds of cores. Intel responded with a category of software called Recognition, Mining, and Synthesis (RMS) applications which require the computational power of tens or hundreds of cores. Recognition applications create models based on what they identify such as a person's face. Mining applications extract one or more instances from a large amount of data. Lastly, synthesis applications allow for prediction and projecting of new environments. An example of where RMS and tera-scale processors are necessary is the creation of sport summaries. Usually sport summaries require hours for a computer to mine through hundreds of thousands of video frames to find short action clips to be shown in the sport summaries. With RMS software and a tera-scale processor, sport summaries could be created in real time during sporting events.<a class="footnote-ref" id="fnref:6" href="#fn:6"><sup>6</sup></a> The Tera-Scale processors also show potential in real-time analysis in fields such as finance which requires a processor that is capable of analyzing immense amounts of data. From Intel's past evolution from single core to multi-core processors, Intel has learned that parallelization is the key to the greater processing power in the future. The Intel Tera-Scale research program is not only focused on creating the multi-cored processors, but also the parallelizing applications of today and in the future. To show their dedication to all aspects of parallel computing, Intel set aside $20 million to establish centers that will research and develop new methods utilize parallel computing in many more applications.<a class="footnote-ref" id="fnref:7" href="#fn:7"><sup>7</sup></a> </p> <h2 id="challenges">Challenges</h2> <p>In early 2005, Intel originally encountered the problem of memory bandwidth. As more cores are added, the memory bandwidth remains the same due to size constrictions, effectively bottlenecking the CPU. They were able to overcome the problem by a process called die stacking. This is a process in which the CPU <a href="/facts/Die_(integrated_circuit)/XWvdlltE">die</a>, flash, and <a href="/facts/Dynamic_random-access_memory/koI9FGo5">DRAM</a> would be stacked on top of each other significantly raising the possible memory bus widths.<a class="footnote-ref" id="fnref:8" href="#fn:8"><sup>8</sup></a> Another challenge that Intel encountered were the physical limitations of electrical buses. A bus bandwidth is the CPU's connection to the outside world and with the current bus bandwidth, it would be unable to keep up with the teraFLOPs performance resulting from tera-scale processors. Intel's research into Silicon Photonics has produced a functional optical bus that can offer superior signaling speed and power efficiency compared to the current buses. These optical buses are an ideal solution to the bus bandwidth limitation for tera-scale processors.<a class="footnote-ref" id="fnref:9" href="#fn:9"><sup>9</sup></a> </p> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>Held, Jim; Bautista, Jerry; Koehl, Sean (2006). "From a Few Cores to Many: A Tera-scale Computing Research Overview" (PDF). White Paper Research at Intel. Intel Corporation. Retrieved 28 October 2014. <a href="http://www.intel.com/content/dam/www/public/us/en/documents/technology-briefs/intel-labs-tera-scale-research-paper.pdf" target="_blank">http://www.intel.com/content/dam/www/public/us/en/documents/technology-briefs/intel-labs-tera-scale-research-paper.pdf</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>Shimpi, Anand Lal. "The Era of Tera: Intel Reveals more about 80-core CPU". AnandTech. Retrieved 29 October 2014. <a href="http://www.anandtech.com/show/2170" target="_blank">http://www.anandtech.com/show/2170</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li> <li id="fn:3"><p>Mattson, Tim. "Using Intel's Single Chip Cloud Computer (SCC)" (PDF). Archived from the original (PDF) on 20 December 2014. Retrieved 11 November 2014. <a href="https://web.archive.org/web/20141220004000/https://communities.intel.com/servlet/JiveServlet/previewBody/19269-102-1-22565/Using%20Intel%E2%80%99s%20Single-Chip%20Cloud%20Computer%20(SCC)%20-%20Intel%2C%20Mattson%2C%20Tutorial.pdf" target="_blank">https://web.archive.org/web/20141220004000/https://communities.intel.com/servlet/JiveServlet/previewBody/19269-102-1-22565/Using%20Intel%E2%80%99s%20Single-Chip%20Cloud%20Computer%20(SCC)%20-%20Intel%2C%20Mattson%2C%20Tutorial.pdf</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li> <li id="fn:4"><p>"Tera-scale Computing Architectural Overview". Intel. Archived from the original on 2014-11-29. Retrieved 2017-01-02. <a href="https://web.archive.org/web/20141129015904/http://www.intel.com/content/www/us/en/research/intel-labs-terascale-computing-demo.html" target="_blank">https://web.archive.org/web/20141129015904/http://www.intel.com/content/www/us/en/research/intel-labs-terascale-computing-demo.html</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li> <li id="fn:5"><p>Shimpi, Anand Lal. "The Era of Tera: Intel Reveals more about 80-core CPU". AnandTech. Retrieved 29 October 2014. <a href="http://www.anandtech.com/show/2170" target="_blank">http://www.anandtech.com/show/2170</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></p></li> <li id="fn:6"><p>Held, Jim; Bautista, Jerry; Koehl, Sean (2006). "From a Few Cores to Many: A Tera-scale Computing Research Overview" (PDF). White Paper Research at Intel. Intel Corporation. Retrieved 28 October 2014. <a href="http://www.intel.com/content/dam/www/public/us/en/documents/technology-briefs/intel-labs-tera-scale-research-paper.pdf" target="_blank">http://www.intel.com/content/dam/www/public/us/en/documents/technology-briefs/intel-labs-tera-scale-research-paper.pdf</a> <a href="#fnref:6" class="footnote-back-ref">↩</a></p></li> <li id="fn:7"><p>Ferguson, Scott. "Microsoft, Intel Earmark $20M for Parallel Computing". eWeek. Retrieved 6 November 2014. <a href="http://www.eweek.com/c/a/IT-Infrastructure/Microsoft-Intel-Earmark-20M-for-Parallel-Computing/" target="_blank">http://www.eweek.com/c/a/IT-Infrastructure/Microsoft-Intel-Earmark-20M-for-Parallel-Computing/</a> <a href="#fnref:7" class="footnote-back-ref">↩</a></p></li> <li id="fn:8"><p>Shimpi, Anand Lal. "The Era of Tera: Intel Reveals more about 80-core CPU". AnandTech. Retrieved 29 October 2014. <a href="http://www.anandtech.com/show/2170" target="_blank">http://www.anandtech.com/show/2170</a> <a href="#fnref:8" class="footnote-back-ref">↩</a></p></li> <li id="fn:9"><p>Shimpi, Anand Lal. "The Era of Tera: Intel Reveals more about 80-core CPU". AnandTech. Retrieved 29 October 2014. <a href="http://www.anandtech.com/show/2170" target="_blank">http://www.anandtech.com/show/2170</a> <a href="#fnref:9" class="footnote-back-ref">↩</a></p></li> </ol>