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BiCMOS
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<h2 id="disadvantages">Disadvantages</h2> <p>Some of the advantages of CMOS fabrication, for example very low cost in mass production, do not transfer directly to BiCMOS fabrication. An inherent difficulty arises from the fact that optimizing both the BJT and MOS components of the process is impossible without adding many extra fabrication steps and consequently increased process cost and reduced yield. Finally, in the area of high performance logic, BiCMOS may never offer as low a power consumption as a foundry process optimized for CMOS alone, due to the potential for higher standby leakage current. </p> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>Puchner, H. (1996). "5.2 BiCMOS Process Technology". Advanced Process Modeling for VLSI Technology (PhD). Institut für Mikroelektronik, Technischen Universität Wien. TUW-101186. <a href="http://www.iue.tuwien.ac.at/phd/puchner/node47_app.html" target="_blank">http://www.iue.tuwien.ac.at/phd/puchner/node47_app.html</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>Puchner 1996, 5.2.1 BiCMOS Process Flow - Puchner, H. (1996). "5.2 BiCMOS Process Technology". Advanced Process Modeling for VLSI Technology (PhD). Institut für Mikroelektronik, Technischen Universität Wien. TUW-101186. <a href="http://www.iue.tuwien.ac.at/phd/puchner/node47_app.html" target="_blank">http://www.iue.tuwien.ac.at/phd/puchner/node47_app.html</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li> <li id="fn:3"><p>"High-performance SiGe BiCMOS solutions" (PDF). Global Foundries. Archived from the original (PDF) on November 30, 2021. <a href="https://web.archive.org/web/20211130165636/https://www.globalfoundries.com/sites/default/files/sige_hp_pb_2020-0212web.pdf" target="_blank">https://web.archive.org/web/20211130165636/https://www.globalfoundries.com/sites/default/files/sige_hp_pb_2020-0212web.pdf</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li> <li id="fn:4"><p>Neil H. E. Weste; David Money Harris (2010). CMOS VLSI Design: A Circuits and Systems Perspective (4th ed.). p. 277. <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li> </ol>