RISC-V assembly language

<h2 id="keywords">Keywords</h2>
<p>Reserved keywords of RISC-V assembly language.
</p>
<ul><li>add</li><li>addi</li><li>and</li><li>andi</li><li>beq</li><li>bge</li><li>bgeu</li><li>blt</li><li>bltu</li><li>bne</li><li>lb</li><li>lbu</li><li>lh</li><li>lhu</li><li>lw</li><li>or</li><li>ori</li><li>sb</li><li>sh</li><li>sll</li><li>slli</li><li>slt</li><li>slti</li><li>sltiu</li><li>sltu</li><li>sra</li><li>srai</li><li>srl</li><li>srli</li><li>sub</li><li>sw</li><li>xor</li><li>xori</li></ul>
<h2 id="mnemonics-and-opcodes">Mnemonics and opcodes</h2>
<p class="note">Further information: <a href="/facts/RISC-V_instruction_listings/uWtfdw0m">RISC-V instruction listings</a></p>
<p>Each instruction in the RISC-V assembly language is represented by a <a href="/facts/Mnemonic/6HfDn0ks">mnemonic</a> which often combines with one or more operands to translate into one or more bytes known as an <a href="/facts/Opcode/UaLMp56C">opcode</a>.
</p>
<h2 id="registers">Registers</h2>
<p class="note">Further information: <a href="/facts/RISC-V/pUSKDat1">RISC-V § Register sets</a></p>
<p>RISC-V processors feature a set of registers that serve as storage for binary data and addresses during program execution. These registers are categorized into integer registers and floating-point registers.
</p>
<h2 id="instruction-types">Instruction types</h2>
<p>RISC-V instructions use variable-length encoding.
</p><p>Extensions:
</p>
<ul><li>atomic instructions</li>
<li>single-precision floating-point</li>
<li>double-precision floating-point</li>
<li>bit manipulation</li>
<li>cryptography</li>
<li>hypervisor</li>
<li>supervisor</li>
<li>packed-SIMD instructions</li>
<li>vector</li></ul>
<h3>Floating-point instructions</h3>
<p>RISC-V assembly language includes instructions for a <a href="/facts/Floating-point_unit/XWTW2AbF">floating-point unit</a> (FPU).
</p>
<h3>SIMD instructions</h3>
<p>These largely perform the same operation in parallel on many values.
</p>
<h2 id="program-flow">Program flow</h2>
<p>The RISC-V assembly has conditional branch instructions based on comparison: beq (equal), bne (not equal), blt (less than, signed), bltu (less than, unsigned), bge (greater than or equal, signed), and bgeu (greater than or equal, unsigned).
</p>
<h2 id="examples">Examples</h2>
.section .text
.globl _start
_start:
	    lui  a1,      %hi(msg)       # load msg(hi)
	    addi a1, a1,  %lo(msg)       # load msg(lo)
	    jalr ra, puts
2:	    j    2b

.section .rodata
msg:
	    .string "Hello World\n"

<h2 id="see-also">See also</h2>
<ul>
<li>Computer programming portal</li></ul>
<ul><li><a href="/facts/Assembly_language/7XuV0cla">Assembly language</a></li>
<li><a href="/facts/RISC-V_instruction_listings/uWtfdw0m">RISC-V instruction listings</a></li>
<li><a href="/facts/CPU_design/HeNbj78g">CPU design</a></li>
<li><a href="/facts/List_of_assemblers/gXrTEcNP">List of assemblers</a></li>
<li><a href="/facts/X86_assembly_language/GTUtvkMm">x86 assembly language</a></li></ul>
<h2 id="external-links">External links</h2>
<ul><li><a href="https://ripes.me/">Ripes</a> –  A graphical processor simulator and assembly editor</li>
<li><a href="https://venus.kvakil.me/">venus</a> –  A instruction set simulator (<a href="https://github.com/kvakil/venus">venus</a> on <a href="/facts/GitHub/n1hNCsc3">GitHub</a>)</li>
<li><a href="https://github.com/TheThirdOne/rars">rars</a> on <a href="/facts/GitHub/n1hNCsc3">GitHub</a></li></ul>

RISC-V assembly language open-in-new

RISC-V assembly language