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<h2 id="overview">Overview</h2> <h3>Instruction sets</h3> <p>At the hardware level, processors contain a number of separate areas of circuitry, or "units", that perform different tasks. Commonly found units include the <a href="/facts/Arithmetic_logic_unit/SgIjPzSc">arithmetic logic unit</a> (ALU) which performs instructions such as addition or comparing two numbers, circuits for reading and writing data to external memory, and small areas of onboard memory to store these values while they are being processed. In most designs, additional high-performance memory, the <a href="/facts/Register_file/NGvqUwe3">register file</a>, is used to store temporary values, not just those needed by the current instruction.<a class="footnote-ref" id="fnref:4" href="#fn:4"><sup>4</sup></a> </p><p>To properly perform an instruction, the various circuits have to be activated in order. For instance, it is not possible to add two numbers if they have not yet been loaded from memory. In <a href="/facts/RISC/aQbGM62p">RISC</a> designs, the proper ordering of these instructions is largely up to the programmer, or at least to the <a href="/facts/Compiler/WNfCDFJe">compiler</a> of the <a href="/facts/Programming_language/cWTYbgWa">programming language</a> they are using. So to add two numbers, for instance, the compiler may output instructions to load one of the values into one register, the second into another, call the addition function in the ALU, and then write the result back out to memory.<a class="footnote-ref" id="fnref:5" href="#fn:5"><sup>5</sup></a> </p><p>As the sequence of instructions needed to complete this higher-level concept, "add these two numbers in memory", may require multiple instructions, this can represent a performance bottleneck if those instructions are stored in <a href="/facts/Main_memory/wPHKFpdx">main memory</a>. Reading those instructions one by one takes time that could be used to read and write the actual data. For this reason, it is common for non-RISC designs to have many different instructions that differ largely on where they store data. For instance, the <a href="/facts/MOS_6502/q9YLwkzm">MOS 6502</a> has eight variations of the addition instruction, ADC, which differ only in where they look to find the two operands.<a class="footnote-ref" id="fnref:6" href="#fn:6"><sup>6</sup></a> </p><p>Using the variation of the instruction, or "<a href="/facts/Opcode/UaLMp56C">opcode</a>", that most closely matches the ultimate operation can reduce the number of instructions to one, saving memory used by the program code and improving performance by leaving the <a href="/facts/Data_bus/R45TKwS7">data bus</a> open for other operations. Internally, however, these instructions are not separate operations, but sequences of the operations the units actually perform. Converting a single instruction read from memory into the sequence of internal actions is the duty of the <a href="/facts/Control_unit/8QRX3lwf">control unit</a>, another unit within the processor.<a class="footnote-ref" id="fnref:7" href="#fn:7"><sup>7</sup></a> </p> <h3>Microcode</h3> <p>The basic idea behind microcode is to replace the custom hardware logic implementing the instruction sequencing with a series of simple instructions run in a "microcode engine" in the processor. Whereas a custom logic system might have a series of diodes and gates that output a series of voltages on various control lines, the microcode engine is connected to these lines instead, and these are turned on and off as the engine reads the microcode instructions in sequence. The microcode instructions are often bit encoded to those lines, for instance, if bit 8 is true, that might mean that the ALU should be paused awaiting data. In this respect microcode is somewhat similar to the paper rolls in a <a href="/facts/Player_piano/UxTEscFk">player piano</a>, where the holes represent which key should be pressed. </p><p>The distinction between custom logic and microcode may seem small, one uses a pattern of diodes and gates to decode the instruction and produce a sequence of signals, whereas the other encodes the signals as microinstructions that are read in sequence to produce the same results. The critical difference is that in a custom logic design, changes to the individual steps require the hardware to be redesigned. Using microcode, all that changes is the code stored in the memory containing the microcode. This makes it much easier to fix problems in a microcode system. It also means that there is no effective limit to the complexity of the instructions, it is only limited by the amount of memory one is willing to use. </p><p>The lowest layer in a computer's software stack is traditionally raw <a href="/facts/Machine_code/bgdQ1Fxf">machine code</a> instructions for the processor. In microcoded processors, fetching and decoding those instructions, and executing them, may be done by microcode. To avoid confusion, each microprogram-related element is differentiated by the <i>micro</i> prefix: microinstruction, microassembler, microprogrammer, etc.<a class="footnote-ref" id="fnref:8" href="#fn:8"><sup>8</sup></a> </p><p>Complex digital processors may also employ more than one (possibly microcode-based) <a href="/facts/Control_unit/8QRX3lwf">control unit</a> in order to delegate sub-tasks that must be performed essentially asynchronously in parallel. For example, the <a href="/facts/VAX_9000/E6n0srpG">VAX 9000</a> has a hardwired IBox unit to fetch and decode instructions, which it hands to a microcoded EBox unit to be executed,<a class="footnote-ref" id="fnref:9" href="#fn:9"><sup>9</sup></a> and the <a href="/facts/VAX_8800/vfedWG31">VAX 8800</a> has both a microcoded IBox and a microcoded EBox.<a class="footnote-ref" id="fnref:10" href="#fn:10"><sup>10</sup></a> </p><p>A high-level programmer, or even an <a href="/facts/Assembly_language/7XuV0cla">assembly language</a> programmer, does not normally see or change microcode. Unlike machine code, which often retains some <a href="/facts/Backward_compatibility/FbHFBu5y">backward compatibility</a> among different processors in a family, microcode only runs on the exact <a href="/facts/Electronic_circuit/IRfQ6Cc2">electronic circuitry</a> for which it is designed, as it constitutes an inherent part of the particular processor design itself. </p> <h3>Design</h3> <p>Engineers normally write the microcode during the design phase of a processor, storing it in a <a href="/facts/Read-only_memory/P9QMuDLH">read-only memory</a> (ROM) or <a href="/facts/Programmable_logic_array/R6lF60jA">programmable logic array</a> (PLA)<a class="footnote-ref" id="fnref:11" href="#fn:11"><sup>11</sup></a> structure, or in a combination of both.<a class="footnote-ref" id="fnref:12" href="#fn:12"><sup>12</sup></a> However, machines also exist that have some or all microcode stored in <a href="/facts/Static_random-access_memory/Pmyo4V5e">static random-access memory</a> (SRAM) or <a href="/facts/Flash_memory/Cn8JsStx">flash memory</a>. This is traditionally denoted as <i>writable <a href="/facts/Control_store/Ts50verp">control store</a></i> in the context of computers, which can be either read-only or <a href="/facts/Read%25E2%2580%2593write_memory/2lHbaw1g">read–write memory</a>. In the latter case, the CPU initialization process loads microcode into the control store from another storage medium, with the possibility of altering the microcode to correct bugs in the instruction set, or to implement new machine instructions. </p> <h3>Microprograms</h3> <p>Microprograms consist of series of microinstructions, which control the CPU at a very fundamental level of hardware circuitry. For example, a single typical <i>horizontal</i> microinstruction might specify the following operations: </p> <ul><li>Connect register 1 to the <i>A</i> side of the <a href="/facts/Arithmetic_logic_unit/SgIjPzSc">ALU</a></li> <li>Connect register 7 to the <i>B</i> side of the ALU</li> <li>Set the ALU to perform <a href="/facts/Two%2527s_complement/xhjYpnsc">two's-complement</a> addition</li> <li>Set the ALU's carry input to zero</li> <li>Store the result value in register 8</li> <li>Update the condition codes from the ALU status flags (<i>negative</i>, <i>zero</i>, <i>overflow</i>, and <i>carry</i>)</li> <li>Microjump to a given <a href="/facts/Program_counter/BxqulBRq">μPC</a> address for the next microinstruction</li></ul> <p>To simultaneously control all processor's features in one cycle, the microinstruction is often wider than 50 bits; e.g., 128 bits on a <a href="/facts/IBM_System%2f360_Model_85/pVoUUagB">360/85</a> with an emulator feature. Microprograms are carefully designed and optimized for the fastest possible execution, as a slow microprogram would result in a slow machine instruction and degraded performance for related application programs that use such instructions. </p> <h2 id="justification">Justification</h2> <p>Microcode was originally developed as a simpler method of developing the control logic for a computer. Initially, CPU <a href="/facts/Instruction_set/8p8vwUeE">instruction sets</a> were <a href="/facts/Hardwired_control_unit/8QRX3lwf">hardwired</a>. Each step needed to fetch, decode, and execute the machine instructions (including any operand address calculations, reads, and writes) was controlled directly by <a href="/facts/Combinational_logic/L1kaaVK5">combinational logic</a> and rather minimal <a href="/facts/Sequential_circuit/Rcs4thlu">sequential</a> state machine circuitry. While such hard-wired processors were very efficient, the need for powerful instruction sets with multi-step addressing and complex operations (<i>see below</i>) made them difficult to design and debug; highly encoded and varied-length instructions can contribute to this as well, especially when very irregular encodings are used. </p><p>Microcode simplified the job by allowing much of the processor's behaviour and programming model to be defined via microprogram routines rather than by dedicated circuitry. Even late in the design process, microcode could easily be changed, whereas hard-wired CPU designs were very cumbersome to change. Thus, this greatly facilitated CPU design. </p><p>From the 1940s to the late 1970s, a large portion of programming was done in <a href="/facts/Assembly_language/7XuV0cla">assembly language</a>; higher-level instructions mean greater programmer productivity, so an important advantage of microcode was the relative ease by which powerful machine instructions can be defined. The ultimate extension of this are "Directly Executable High Level Language" designs, in which each statement of a high-level language such as <a href="/facts/PL%2fI/469mVYgd">PL/I</a> is entirely and directly executed by microcode, without compilation. The <a href="/facts/IBM_Future_Systems_project/ohJpmw9F">IBM Future Systems project</a> and <a href="/facts/Data_General/EEABV3Gu">Data General</a> Fountainhead Processor are examples of this. During the 1970s, CPU speeds grew more quickly than memory speeds and numerous techniques such as <a href="/facts/Direct_memory_access/DWuVgclV">memory block transfer</a>, <a href="/facts/Prefetching/utYYSY1q">memory pre-fetch</a> and <a href="/facts/Multi-level_cache/x8BYFcdv">multi-level caches</a> were used to alleviate this. High-level machine instructions, made possible by microcode, helped further, as fewer more complex machine instructions require less memory bandwidth. For example, an operation on a character string can be done as a single machine instruction, thus avoiding multiple instruction fetches. </p><p>Architectures with instruction sets implemented by complex microprograms included the <a href="/facts/IBM/QszA7nwd">IBM</a> <a href="/facts/System%2f360/7znvpy4K">System/360</a> and <a href="/facts/Digital_Equipment_Corporation/ztxs6keA">Digital Equipment Corporation</a> <a href="/facts/VAX/N3r13IHH">VAX</a>. The approach of increasingly complex microcode-implemented instruction sets was later called <a href="/facts/Complex_instruction_set_computer/Ucvyh2xq">complex instruction set computer</a> (CISC). An alternate approach, used in many <a href="/facts/Microprocessor/Fx9CaQht">microprocessors</a>, is to use one or more <a href="/facts/Programmable_logic_array/R6lF60jA">programmable logic array</a> (PLA) or <a href="/facts/Read-only_memory/P9QMuDLH">read-only memory</a> (ROM) (instead of combinational logic) mainly for instruction decoding, and let a simple state machine (without much, or any, microcode) do most of the sequencing. The <a href="/facts/MOS_Technology_6502/q9YLwkzm">MOS Technology 6502</a> is an example of a microprocessor using a PLA for instruction decode and sequencing. The PLA is visible in photomicrographs of the chip,<a class="footnote-ref" id="fnref:13" href="#fn:13"><sup>13</sup></a> and its operation can be seen in the <a href="/facts/Transistor/Bmr8zwL0">transistor</a>-level simulation. </p><p>Microprogramming is still used in modern CPU designs. In some cases, after the microcode is debugged in simulation, logic functions are substituted for the control store. Logic functions are often faster and less expensive than the equivalent microprogram memory. </p> <h3>Benefits</h3> <p>A processor's microprograms operate on a more primitive, totally different, and much more hardware-oriented architecture than the assembly instructions visible to normal programmers. In coordination with the hardware, the microcode implements the programmer-visible architecture. The underlying hardware need not have a fixed relationship to the visible architecture. This makes it easier to implement a given instruction set architecture on a wide variety of underlying hardware micro-architectures. </p><p>The IBM System/360 has a 32-bit architecture with 16 general-purpose registers, but most of the System/360 implementations use hardware that implements a much simpler underlying microarchitecture; for example, the <a href="/facts/IBM_System%2f360_Model_30/Jr2vfIjC">System/360 Model 30</a> has 8-bit data paths to the arithmetic logic unit (ALU) and main memory and implemented the general-purpose registers in a special unit of higher-speed <a href="/facts/Magnetic-core_memory/4TFIXSNd">core memory</a>, and the <a href="/facts/IBM_System%2f360_Model_40/H4trg2ty">System/360 Model 40</a> has 8-bit data paths to the ALU and 16-bit data paths to main memory and also implemented the general-purpose registers in a special unit of higher-speed core memory. The <a href="/facts/IBM_System%2f360_Model_50/GdQ5YhT2">Model 50</a> has full 32-bit data paths and implements the general-purpose registers in a special unit of higher-speed core memory.<a class="footnote-ref" id="fnref:14" href="#fn:14"><sup>14</sup></a> The Model 65 through the Model 195 have larger data paths and implement the general-purpose registers in faster transistor circuits. In this way, microprogramming enabled IBM to design many System/360 models with substantially different hardware and spanning a wide range of cost and performance, while making them all architecturally compatible. This dramatically reduces the number of unique system software programs that must be written for each model. </p><p>A similar approach was used by Digital Equipment Corporation (DEC) in their VAX family of computers. As a result, different VAX processors use different microarchitectures, yet the programmer-visible architecture does not change. </p><p>Microprogramming also reduces the cost of field changes to correct defects (<a href="/facts/Computer_bug/I1uSXySv">bugs</a>) in the processor; a bug can often be fixed by replacing a portion of the microprogram rather than by changes being made to <a href="/facts/Hardware_logic/fKcrTv2f">hardware logic</a> and wiring. </p> <h2 id="history">History</h2> <h3>Early examples</h3> <p>In 1947, the design of the <a href="/facts/Whirlwind_(computer)/IbG8pxYt">MIT Whirlwind</a> introduced the concept of a control store as a way to simplify computer design and move beyond <i><a href="/facts/Ad_hoc/IYxx5Ha8">ad hoc</a></i> methods. The control store is a <a href="/facts/Diode_matrix/3MPPVB8s">diode matrix</a>: a two-dimensional lattice, where one dimension accepts "control time pulses" from the CPU's internal clock, and the other connects to control signals on gates and other circuits. A "pulse distributor" takes the pulses generated by the <a href="/facts/CPU_clock/w055Woaj">CPU clock</a> and breaks them up into eight separate time pulses, each of which activates a different row of the lattice. When the row is activated, it activates the control signals connected to it.<a class="footnote-ref" id="fnref:15" href="#fn:15"><sup>15</sup></a> </p><p>In 1951, <a href="/facts/Maurice_Wilkes/2RJ58EKc">Maurice Wilkes</a><a class="footnote-ref" id="fnref:16" href="#fn:16"><sup>16</sup></a> enhanced this concept by adding <i>conditional execution</i>, a concept akin to a <a href="/facts/Conditional_(programming)/8gDQTqUD">conditional</a> in computer software. His initial implementation consisted of a pair of matrices: the first one generated signals in the manner of the Whirlwind control store, while the second matrix selected which row of signals (the microprogram instruction word, so to speak) to invoke on the next cycle. Conditionals were implemented by providing a way that a single line in the control store could choose from alternatives in the second matrix. This made the control signals conditional on the detected internal signal. Wilkes coined the term <i>microprogramming</i> to describe this feature and distinguish it from a simple control store. </p> <h3>The 360</h3> <p class="note">Main article: <a href="/facts/System%2f360/7znvpy4K">System/360</a></p> <p>Microcode remained relatively rare in computer design as the cost of the ROM needed to store the code was not significantly different from the cost of custom control logic. This changed through the early 1960s with the introduction of mass-produced <a href="/facts/Core_memory/4TFIXSNd">core memory</a> and <a href="/facts/Core_rope/fFDpRmJs">core rope</a>, which was far less expensive than dedicated logic based on diode arrays or similar solutions. The first to take real advantage of this was <a href="/facts/IBM/QszA7nwd">IBM</a> in their 1964 <a href="/facts/System%2f360/7znvpy4K">System/360</a> series. This allowed the machines to have a very complex instruction set, including operations that matched high-level language constructs like formatting binary values as decimal strings, encoding the complex series of internal steps needed for this task in low cost memory.<a class="footnote-ref" id="fnref:17" href="#fn:17"><sup>17</sup></a> </p><p>But the real value in the 360 line was that one could build a series of machines that were completely different internally, yet run the same ISA. For a low-end machine, one might use an 8-bit ALU that requires multiple cycles to complete a single 32-bit addition, while a higher end machine might have a full 32-bit ALU that performs the same addition in a single cycle. These differences could be implemented in control logic, but the cost of implementing a completely different decoder for each machine would be prohibitive. Using microcode meant all that changed was the code in the ROM. For instance, one machine might include a <a href="/facts/Floating_point_unit/XWTW2AbF">floating point unit</a> and thus its microcode for multiplying two numbers might be only a few lines line, whereas on the same machine without the FPU this would be a program that did the same using multiple additions, and all that changed was the ROM.<a class="footnote-ref" id="fnref:18" href="#fn:18"><sup>18</sup></a> </p><p>The outcome of this design was that customers could use a low-end model of the family to develop their software, knowing that if more performance was ever needed, they could move to a faster version and nothing else would change. This lowered the barrier to entry and the 360 was a runaway success. By the end of the decade, the use of microcode was <i>de rigueur</i> across the mainframe industry. </p> <h3>Moving up the line</h3> <p>Early <a href="/facts/Minicomputer/g8hvpQxe">minicomputers</a> were far too simple to require microcode, and were more similar to earlier mainframes in terms of their instruction sets and the way they were decoded. But it was not long before their designers began using more powerful <a href="/facts/Integrated_circuit/fjn6vg7C">integrated circuits</a> that allowed for more complex ISAs. By the mid-1970s, most new minicomputers and <a href="/facts/Superminicomputer/MkAxa8fs">superminicomputers</a> were using microcode as well, such as most models of the <a href="/facts/PDP-11/9HkGUzFn">PDP-11</a> and, most notably, most models of the <a href="/facts/VAX/N3r13IHH">VAX</a>, which included high-level instruction not unlike those found in the 360.<a class="footnote-ref" id="fnref:19" href="#fn:19"><sup>19</sup></a> </p><p>The same basic evolution occurred with <a href="/facts/Microprocessor/Fx9CaQht">microprocessors</a> as well. Early designs were extremely simple, and even the more powerful 8-bit designs of the mid-1970s like the <a href="/facts/Zilog_Z80/Jeqe2h55">Zilog Z80</a> had instruction sets that were simple enough to be implemented in dedicated logic. By this time, the control logic could be patterned into the same die as the CPU, making the difference in cost between ROM and logic less of an issue. However, it was not long before these companies were also facing the problem of introducing higher-performance designs but still wanting to offer <a href="/facts/Backward_compatibility/FbHFBu5y">backward compatibility</a>. Among early examples of microcode in micros was the <a href="/facts/Intel_8086/sS9dlSdK">Intel 8086</a>.<a class="footnote-ref" id="fnref:20" href="#fn:20"><sup>20</sup></a> </p><p>Among the ultimate implementations of microcode in microprocessors is the <a href="/facts/Motorola_68000/3p2wt2D6">Motorola 68000</a>. This offered a highly <a href="/facts/Orthogonal_instruction_set/1eF24vXc">orthogonal instruction set</a> with a wide variety of <a href="/facts/Addressing_mode/g78wINgK">addressing modes</a>, all implemented in microcode. This did not come without cost, according to early articles, about 20% of the chip's surface area (and thus cost) is the microcode system<a class="footnote-ref" id="fnref:21" href="#fn:21"><sup>21</sup></a> and of the systems 68,000 transistors were part of the microcode system. </p> <h3>RISC enters</h3> <p>While companies continued to compete on the complexity of their instruction sets, and the use of microcode to implement these was unquestioned, in the mid-1970s an internal project in IBM was raising serious questions about the entire concept. As part of a project to develop a high-performance all-digital <a href="/facts/Telephone_switch/PaRpGm8I">telephone switch</a>, a team led by <a href="/facts/John_Cocke_(computer_scientist)/u2q0rtyw">John Cocke</a> began examining huge volumes of performance data from their customer's 360 (and <a href="/facts/System%2f370/TRo1jaFw">System/370</a>) programs. This led them to notice a curious pattern: when the ISA presented multiple versions of an instruction, the <a href="/facts/Compiler/WNfCDFJe">compiler</a> almost always used the simplest one, instead of the one most directly representing the code. They learned that this was because those instructions were always implemented in hardware, and thus run the fastest. Using the other instruction might offer higher performance on some machines, but there was no way to know what machine they were running on. This defeated the purpose of using microcode in the first place, which was to hide these distinctions.<a class="footnote-ref" id="fnref:22" href="#fn:22"><sup>22</sup></a> </p><p>The team came to a radical conclusion: "Imposing microcode between a computer and its users imposes an expensive overhead in performing the most frequently executed instructions."<a class="footnote-ref" id="fnref:23" href="#fn:23"><sup>23</sup></a> </p><p>The result of this discovery was what is today known as the <a href="/facts/RISC/aQbGM62p">RISC</a> concept. The complex microcode engine and its associated ROM is reduced or eliminated completely, and those circuits instead dedicated to things like additional registers or a wider ALU, which increases the performance of every program. When complex sequences of instructions are needed, this is left to the compiler, which is the entire purpose of using a compiler in the first place. The basic concept was soon picked up by university researchers in California, where simulations suggested such designs would trivially outperform even the fastest conventional designs. It was one such project, at the <a href="/facts/University_of_California%2c_Berkeley/MXVEjklr">University of California, Berkeley</a>, that introduced the term RISC. </p><p>The industry responded to the concept of RISC with both confusion and hostility, including a famous dismissive article by the VAX team at Digital.<a class="footnote-ref" id="fnref:24" href="#fn:24"><sup>24</sup></a> A major point of contention was that implementing the instructions outside of the processor meant it would spend much more time reading those instructions from memory, thereby slowing overall performance no matter how fast the CPU itself ran.<a class="footnote-ref" id="fnref:25" href="#fn:25"><sup>25</sup></a> Proponents pointed out that simulations clearly showed the number of instructions was not much greater, especially when considering compiled code.<a class="footnote-ref" id="fnref:26" href="#fn:26"><sup>26</sup></a> </p><p>The debate raged until the first commercial RISC designs emerged in the second half of the 1980s, which easily outperformed the most complex designs from other companies. By the late 1980s it was over; even DEC was abandoning microcode for their <a href="/facts/DEC_Alpha/4eN7LuXG">DEC Alpha</a> designs, and CISC processors switched to using hardwired circuitry, rather than microcode, to perform many functions. For example, the <a href="/facts/Intel_80486/2zfEAXAw">Intel 80486</a> uses hardwired circuitry to fetch and decode instructions, using microcode only to execute instructions; register-register move and arithmetic instructions required only one microinstruction, allowing them to be completed in one clock cycle.<a class="footnote-ref" id="fnref:27" href="#fn:27"><sup>27</sup></a> The <a href="/facts/Pentium_Pro/mTAN64fo">Pentium Pro</a>'s fetch and decode hardware fetches instructions and decodes them into series of micro-operations that are passed on to the execution unit, which schedules and executes the micro-operations, possibly doing so <a href="/facts/Out-of-order_execution/bM0dQM8m">out-of-order</a>. Complex instructions are implemented by microcode that consists of predefined sequences of micro-operations.<a class="footnote-ref" id="fnref:28" href="#fn:28"><sup>28</sup></a> </p><p>Some processor designs use machine code that runs in a special mode, with special instructions, available only in that mode, that have access to processor-dependent hardware, to implement some low-level features of the instruction set. The DEC Alpha, a pure RISC design, used <a href="/facts/PALcode/7EqvwKYF">PALcode</a> to implement features such as <a href="/facts/Translation_lookaside_buffer/vvwGkfvD">translation lookaside buffer</a> (TLB) miss handling and interrupt handling,<a class="footnote-ref" id="fnref:29" href="#fn:29"><sup>29</sup></a> as well as providing, for Alpha-based systems running <a href="/facts/OpenVMS/rAnHAgpD">OpenVMS</a>, instructions requiring interlocked memory access that are similar to instructions provided by the <a href="/facts/VAX/N3r13IHH">VAX</a> architecture.<a class="footnote-ref" id="fnref:30" href="#fn:30"><sup>30</sup></a> CMOS <a href="/facts/IBM_System%2f390/lzkp2UE5">IBM System/390</a> CPUs, starting with the G4 processor, and <a href="/facts/Z%2fArchitecture/FcKYkGn9">z/Architecture</a> CPUs use <a href="/facts/Millicode/KwgVHFLW">millicode</a> to implement some instructions.<a class="footnote-ref" id="fnref:31" href="#fn:31"><sup>31</sup></a> </p> <h2 id="examples">Examples</h2> <ul><li>The <a href="/facts/Analytical_engine/Ts9xduLI">Analytical engine</a> envisioned by <a href="/facts/Charles_Babbage/T3jklQcd">Charles Babbage</a> uses <a href="/facts/Read-only_memory/P9QMuDLH">pegs inserted into rotating drums</a> to store its internal procedures.</li> <li>The <a href="/facts/EMIDEC_1100/9Y0XoWGG">EMIDEC 1100</a><a class="footnote-ref" id="fnref:32" href="#fn:32"><sup>32</sup></a> reputedly uses a hard-wired control store consisting of wires threaded through ferrite cores, known as "the laces".</li> <li>Most models of the IBM System/360 series are microprogrammed: <ul><li>The <a href="/facts/IBM_System%2f360_Model_25/Fa4Gwmj9">Model 25</a> is unique among System/360 models in using the top 16 K bytes of core storage to hold the control storage for the microprogram. The 2025 uses a 16-bit microarchitecture with seven control words (or microinstructions). After system maintenance or when changing operating mode, the microcode is loaded from the card reader, tape, or other device.<a class="footnote-ref" id="fnref:33" href="#fn:33"><sup>33</sup></a> The <a href="/facts/IBM_1410/JnYxAHWE">IBM 1410</a> emulation for this model is loaded this way.</li> <li>The <a href="/facts/IBM_2030/Jr2vfIjC">Model 30</a> uses an 8-bit microarchitecture with only a few hardware registers; everything that the programmer saw is emulated by the microprogram. The microcode for this model is also held on special punched cards, which are stored inside the machine in a dedicated reader per card, called "CROS" units (Capacitor Read-Only Storage).<a class="footnote-ref" id="fnref:34" href="#fn:34"><sup>34</sup></a>: 2–5 Another CROS unit is added for machines ordered with 1401/1440/1460 emulation<a class="footnote-ref" id="fnref:35" href="#fn:35"><sup>35</sup></a>: 4–29 and for machines ordered with 1620 emulation.<a class="footnote-ref" id="fnref:36" href="#fn:36"><sup>36</sup></a>: 4–75 </li> <li>The <a href="/facts/IBM_System%2f360_Model_40/H4trg2ty">Model 40</a> uses 56-bit control words. The 2040 box implements both the System/360 main processor and the multiplex channel (the I/O processor). This model uses <i>TROS</i> dedicated readers similar to <i>CROS</i> units, but with an inductive pickup (Transformer Read-only Store).</li> <li>The <a href="/facts/IBM_System%2f360_Model_50/GdQ5YhT2">Model 50</a> has two internal datapaths which operated in parallel: a 32-bit datapath used for arithmetic operations, and an 8-bit data path used in some logical operations. The control store uses 90-bit microinstructions.</li> <li>The <a href="/facts/IBM_System%2f360_Model_85/pVoUUagB">Model 85</a> has separate instruction fetch (I-unit) and execution (E-unit) to provide high performance. The I-unit is hardware controlled. The E-unit is microprogrammed; the control words are 108 bits wide on a basic 360/85 and wider if an emulator feature is installed.</li></ul></li> <li>The <a href="/facts/NCR_315/P4jCBhRE">NCR 315</a> is microprogrammed with hand wired ferrite cores (a <a href="/facts/Read-only_memory/P9QMuDLH">ROM</a>) pulsed by a sequencer with conditional execution. Wires routed through the cores are enabled for various data and logic elements in the processor.</li> <li>The Digital Equipment Corporation <a href="/facts/PDP-9/Jnq93YTI">PDP-9</a> processor, KL10 and KS10 <a href="/facts/PDP-10/zlfam4wk">PDP-10</a> processors, and <a href="/facts/PDP-11/9HkGUzFn">PDP-11</a> processors with the exception of the PDP-11/20, are microprogrammed.<a class="footnote-ref" id="fnref:37" href="#fn:37"><sup>37</sup></a></li> <li>Most <a href="/facts/Data_General_Eclipse/X4d6UhA5">Data General Eclipse</a> minicomputers are microprogrammed. The task of writing microcode for the <a href="/facts/Data_General_Eclipse_MV%2f8000/RQsQBvPj">Eclipse MV/8000</a> is detailed in the Pulitzer Prize-winning book titled <i><a href="/facts/The_Soul_of_a_New_Machine/9mmTRNts">The Soul of a New Machine</a></i>.</li> <li>Many systems from <a href="/facts/Burroughs_Corporation/NAEwIvpU">Burroughs</a> are microprogrammed:</li></ul> <ul><li>The B700 "microprocessor" execute application-level opcodes using sequences of 16-bit microinstructions stored in main memory; each of these is either a register-load operation or mapped to a single 56-bit "nanocode" instruction stored in read-only memory. This allows comparatively simple hardware to act either as a mainframe peripheral controller or to be packaged as a standalone computer.</li> <li>The <a href="/facts/B1700/80aExR2b">B1700</a> is implemented with radically different hardware including bit-addressable main memory but has a similar multi-layer organisation. The operating system preloads the interpreter for whatever language is required. These interpreters present different virtual machines for <a href="/facts/COBOL/wVnhqs0k">COBOL</a>, <a href="/facts/Fortran/m1KqjcMU">Fortran</a>, etc.</li></ul> <ul><li><a href="/facts/Microdata_Corporation/L7xIm5MU">Microdata</a> produced computers in which the microcode is accessible to the user; this allows the creation of custom assembler level instructions. Microdata's <a href="/facts/Pick_operating_system/LSXLknzu">Reality</a> operating system design makes extensive use of this capability.</li> <li>The <a href="/facts/Xerox_Alto/6pjFTD0A">Xerox Alto</a> workstation used a microcoded design but, unlike many computers, the microcode engine is not hidden from the programmer in a layered design. Applications take advantage of this to accelerate performance.</li> <li>The <a href="/facts/IBM_System%2f38/lwEK6d2A">IBM System/38</a> is described as having both <a href="/facts/IBM_System%2f38/lwEK6d2A">horizontal and vertical microcode</a>.<a class="footnote-ref" id="fnref:38" href="#fn:38"><sup>38</sup></a> In practice, the processor implements an instruction set architecture named the <i>Internal Microprogrammed Interface</i> (IMPI) using a horizontal microcode format. The so-called vertical microcode layer implements the System/38's hardware-independent <a href="/facts/IBM_System%2f38/lwEK6d2A">Machine Interface</a> (MI) instruction set by translating MI code to IMPI code and executing it. Prior to the introduction of the <a href="/facts/IBM_RS64/8zeWM0vA">IBM RS64</a> processor line, early <a href="/facts/IBM_AS%2f400/BWYaNnqe">IBM AS/400</a> systems used the same architecture.<a class="footnote-ref" id="fnref:39" href="#fn:39"><sup>39</sup></a></li> <li>The <a href="/facts/Nintendo_64/p1rI4VQ2">Nintendo 64</a>'s <a href="/facts/Reality_Coprocessor/o2R4Rzjd">Reality Coprocessor</a> (RCP), which serves as the console's <a href="/facts/Graphics_processing_unit/PTK1RQVp">graphics processing unit</a> and audio processor, utilizes microcode; it is possible to implement new effects or tweak the processor to achieve the desired output. Some notable examples of custom RCP microcode include the high-resolution graphics, particle engines, and unlimited draw distances found in <a href="/facts/Factor_5/KVyzb6mF">Factor 5</a>'s <i><a href="/facts/Indiana_Jones_and_the_Infernal_Machine/U9QqwaoF">Indiana Jones and the Infernal Machine</a></i>, <i><a href="/facts/Star_Wars%3a_Rogue_Squadron/SJnrm6UM">Star Wars: Rogue Squadron</a></i>, and <i><a href="/facts/Star_Wars%3a_Battle_for_Naboo/3KfSQXGa">Star Wars: Battle for Naboo</a></i>;<a class="footnote-ref" id="fnref:40" href="#fn:40"><sup>40</sup></a><a class="footnote-ref" id="fnref:41" href="#fn:41"><sup>41</sup></a> and the <a href="/facts/Full_motion_video/DGyQ52z7">full motion video</a> playback found in <a href="/facts/Rockstar_San_Diego/n1Bnp3hx">Angel Studios</a>' <i><a href="/facts/Resident_Evil_2/Pe56j27N">Resident Evil 2</a></i>.<a class="footnote-ref" id="fnref:42" href="#fn:42"><sup>42</sup></a></li></ul> <p class="note">Further information on Nintendo 64 microcode: <a href="/facts/Nintendo_64_programming_characteristics/3XqgBvbV">Nintendo 64 programming characteristics</a> and <a href="/facts/Nintendo_64_Game_Pak/ProyL7vU">Nintendo 64 Game Pak</a></p> <ul><li>The VU0 and VU1 vector units in the <a href="/facts/Sony/7x4tCtBd">Sony</a> <a href="/facts/PlayStation_2/gbFBT7AX">PlayStation 2</a> are microprogrammable; in fact, VU1 is only accessible via microcode for the first several generations of the SDK.</li> <li>The MicroCore Labs <a href="http://www.microcorelabs.com/mcl86.html">MCL86</a> <a href="https://web.archive.org/web/20161103224205/http://www.microcorelabs.com/mcl86.html">Archived</a> 2016-11-03 at the <a href="/facts/Wayback_Machine/nmQ3a6JC">Wayback Machine</a> , <a href="http://www.microcorelabs.com/mcl51.html">MCL51</a> <a href="https://web.archive.org/web/20170202042033/http://www.microcorelabs.com/mcl51.html">Archived</a> 2017-02-02 at the <a href="/facts/Wayback_Machine/nmQ3a6JC">Wayback Machine</a> and <a href="http://www.microcorelabs.com/mcl65.html">MCL65</a> <a href="https://web.archive.org/web/20181221000146/http://www.microcorelabs.com/mcl65.html">Archived</a> 2018-12-21 at the <a href="/facts/Wayback_Machine/nmQ3a6JC">Wayback Machine</a> are examples of highly encoded "vertical" microsequencer implementations of the Intel 8086/8088, 8051, and MOS 6502.</li> <li>The <a href="http://www.bitsavers.org/pdf/digitalScientific/">Digital Scientific Corp.</a> Meta 4 Series 16 computer system was a user-microprogammable system first available in 1970. The microcode had a primarily vertical style with 32-bit microinstructions.<a class="footnote-ref" id="fnref:43" href="#fn:43"><sup>43</sup></a> The instructions were stored on replaceable program boards with a grid of bit positions. One (1) bits were represented by small metal squares that were sensed by amplifiers, zero (0) bits by the absence of the squares.<a class="footnote-ref" id="fnref:44" href="#fn:44"><sup>44</sup></a> The system could be configured with up to 4K 16-bit words of microstore. One of Digital Scientific's products was an emulator for the <a href="/facts/IBM_1130/zQ9Acd05">IBM 1130</a>.<a class="footnote-ref" id="fnref:45" href="#fn:45"><sup>45</sup></a><a class="footnote-ref" id="fnref:46" href="#fn:46"><sup>46</sup></a></li> <li>The <a href="/facts/MCP-1600/qq7t6Hx2">MCP-1600</a> is a <a href="/facts/Microprocessor/Fx9CaQht">microprocessor</a> made by <a href="/facts/Western_Digital/Yqc4qS3l">Western Digital</a> from 1975 through the early 1980s. It was used to implement three different computer architectures in microcode: the <a href="/facts/Pascal_MicroEngine/yp6yjahr">Pascal MicroEngine</a>, the <a href="/facts/WD16/07sHjgJQ">WD16</a>, and the <a href="/facts/Digital_Equipment_Corporation/ztxs6keA">DEC</a> <a href="/facts/PDP-11/9HkGUzFn">LSI-11</a>, a cost-reduced PDP-11.<a class="footnote-ref" id="fnref:47" href="#fn:47"><sup>47</sup></a></li> <li>Earlier <a href="/facts/X86/Kypq5fgu">x86</a> processors are fully microcoded. x86 processors implemented <a href="/facts/Patchable_microcode/Ts50verp">patchable microcode</a> (patch by <a href="/facts/BIOS/2RY3dzQe">BIOS</a> or <a href="/facts/Operating_system/8XTuvMh2">operating system</a>) since <a href="/facts/P6_(microarchitecture)/e8zEuP4E">Intel P6 microarchitecture</a> and <a href="/facts/Athlon/3BFQu05f">AMD K7 microarchitecture</a>. Such processors implemented microcode ROM and microcode SRAM in their silicon.</li> <li>Many <a href="/facts/Video_card/bcKfPyFt">video cards</a> and <a href="/facts/Network_interface_controller/wyf5FR29">network interface controllers</a> implement patchable microcode (patch by operating system). Such microcode is patched to device's <a href="/facts/Static_random-access_memory/Pmyo4V5e">SRAM</a> or <a href="/facts/DRAM/koI9FGo5">DRAM</a>, for example, <a href="/facts/GDDR_SDRAM/7qXy4dzW">GDDR SDRAM</a> of a video card.</li></ul> <h2 id="implementation">Implementation</h2> <p>Each microinstruction in a microprogram provides the bits that control the functional elements that internally compose a CPU. The advantage over a hard-wired CPU is that internal CPU control becomes a specialized form of a computer program. Microcode thus transforms a complex electronic design challenge (the control of a CPU) into a less complex programming challenge. To take advantage of this, a CPU is divided into several parts: </p> <ul><li>An <a href="/facts/I-unit/g9A4MCUT">I-unit</a> may decode instructions in hardware and determine the microcode address for processing the instruction in parallel with the <a href="/facts/Execution_unit/uvg54JcX">E-unit</a>.</li> <li>A <a href="/facts/Microsequencer/7v30jEIr">microsequencer</a> picks the next word of the control store. A sequencer is mostly a counter, but usually also has some way to jump to a different part of the control store depending on some data, usually data from the <a href="/facts/Instruction_register/IBHBHtPl">instruction register</a> and always some part of the control store. The simplest sequencer is just a register loaded from a few bits of the control store.</li> <li>A <a href="/facts/Processor_register/32RvbUdz">register</a> set is a fast memory containing the data of the central processing unit. It may include registers visible to application programs, such as <a href="/facts/General-purpose_registers/32RvbUdz">general-purpose registers</a> and the <a href="/facts/Program_counter/BxqulBRq">program counter</a>, and may also include other registers that are not easily accessible to the application programmer. Often the register set is a triple-ported <a href="/facts/Register_file/NGvqUwe3">register file</a>; that is, two registers can be read, and a third written at the same time.</li> <li>An <a href="/facts/Arithmetic_and_logic_unit/SgIjPzSc">arithmetic and logic unit</a> performs calculations, usually addition, logical negation, a right shift, and logical AND. It often performs other functions, as well.</li></ul> <p>There may also be a <a href="/facts/Memory_address_register/TJokLCFI">memory address register</a> and a <a href="/facts/Memory_data_register/oeh8blI5">memory data register</a>, used to access the main <a href="/facts/Computer_storage/wPHKFpdx">computer storage</a>. Together, these elements form an "<a href="/facts/Execution_unit/uvg54JcX">execution unit</a>". Most modern <a href="/facts/Central_processing_unit/Jxp1bqMV">CPUs</a> have several execution units. Even simple computers usually have one unit to read and write memory, and another to execute user code. These elements could often be brought together as a single chip. This chip comes in a fixed width that would form a "slice" through the execution unit. These are known as "<a href="/facts/Bit_slicing/lf0t4CB3">bit slice</a>" chips. The <a href="/facts/AMD_Am2900/zTN3yqdm">AMD Am2900</a> family is one of the best known examples of bit slice elements.<a class="footnote-ref" id="fnref:48" href="#fn:48"><sup>48</sup></a> The parts of the execution units and the whole execution units are interconnected by a bundle of wires called a <a href="/facts/Computer_bus/R45TKwS7">bus</a>. </p><p>Programmers develop microprograms, using basic software tools. A <a href="/facts/Microassembler/RHId3WvQ">microassembler</a> allows a programmer to define the table of bits symbolically. Because of its close relationship to the underlying architecture, "microcode has several properties that make it difficult to generate using a compiler."<a class="footnote-ref" id="fnref:49" href="#fn:49"><sup>49</sup></a> A <a href="/facts/Simulator/Q4QJV1oI">simulator</a> program is intended to execute the bits in the same way as the electronics, and allows much more freedom to debug the microprogram. After the microprogram is finalized, and extensively tested, it is sometimes used as the input to a computer program that constructs logic to produce the same data. This program is similar to those used to optimize a <a href="/facts/Programmable_logic_device/7dIVypm9">programmable logic array</a>. Even without fully optimal logic, heuristically optimized logic can vastly reduce the number of transistors from the number needed for a <a href="/facts/Read-only_memory/P9QMuDLH">read-only memory</a> (ROM) control store. This reduces the cost to produce, and the electricity used by, a CPU. </p><p>Microcode can be characterized as <i>horizontal</i> or <i>vertical</i>, referring primarily to whether each microinstruction controls CPU elements with little or no decoding (horizontal microcode)<a class="footnote-ref" id="fnref:50" href="#fn:50"><sup>50</sup></a> or requires extensive decoding by <a href="/facts/Combinatorial_logic/L1kaaVK5">combinatorial logic</a> before doing so (vertical microcode). Consequently, each horizontal microinstruction is wider (contains more bits) and occupies more storage space than a vertical microinstruction. </p> <h3>Horizontal microcode</h3> <p>"Horizontal microcode has several discrete micro-operations that are combined in a single microinstruction for simultaneous operation."<a class="footnote-ref" id="fnref:51" href="#fn:51"><sup>51</sup></a> Horizontal microcode is typically contained in a fairly wide control store; it is not uncommon for each word to be 108 bits or more. On each tick of a sequencer clock a microcode word is read, decoded, and used to control the functional elements that make up the CPU. </p><p>In a typical implementation a horizontal microprogram word comprises fairly tightly defined groups of bits. For example, one simple arrangement might be: </p> <table><tbody><tr><td>Register source A</td><td>Register source B</td><td>Destination register</td><td><a href="/facts/Arithmetic_and_logic_unit/SgIjPzSc">Arithmetic and logic unit</a> operation</td><td>Type of jump</td><td>Jump address</td></tr></tbody></table> <p>For this type of micromachine to implement a JUMP instruction with the address following the opcode, the microcode might require two clock ticks. The engineer designing it would write microassembler source code looking something like this: </p> # Any line starting with a number-sign is a comment # This is just a label, the ordinary way assemblers symbolically represent a # memory address. InstructionJUMP: # To prepare for the next instruction, the instruction-decode microcode has already # moved the program counter to the memory address register. This instruction fetches # the target address of the jump instruction from the memory word following the # jump opcode, by copying from the memory data register to the memory address register. # This gives the memory system two clock ticks to fetch the next # instruction to the memory data register for use by the instruction decode. # The sequencer instruction "next" means just add 1 to the control word address. MDR, NONE, MAR, COPY, NEXT, NONE # This places the address of the next instruction into the PC. # This gives the memory system a clock tick to finish the fetch started on the # previous microinstruction. # The sequencer instruction is to jump to the start of the instruction decode. MAR, 1, PC, ADD, JMP, InstructionDecode # The instruction decode is not shown, because it is usually a mess, very particular # to the exact processor being emulated. Even this example is simplified. # Many CPUs have several ways to calculate the address, rather than just fetching # it from the word following the op-code. Therefore, rather than just one # jump instruction, those CPUs have a family of related jump instructions. <p>For each tick it is common to find that only some portions of the CPU are used, with the remaining groups of bits in the microinstruction being no-ops. With careful design of hardware and microcode, this property can be exploited to parallelise operations that use different areas of the CPU; for example, in the case above, the ALU is not required during the first tick, so it could potentially be used to complete an earlier arithmetic instruction. </p> <h3>Vertical microcode</h3> <p>In vertical microcode, each microinstruction is significantly encoded, that is, the bit fields generally pass through intermediate combinatory logic that, in turn, generates the control and sequencing signals for internal CPU elements (ALU, registers, etc.). This is in contrast with horizontal microcode, in which the bit fields either directly produce the control and sequencing signals or are only minimally encoded. Consequently, vertical microcode requires smaller instruction lengths and less storage, but requires more time to decode, resulting in a slower CPU clock.<a class="footnote-ref" id="fnref:52" href="#fn:52"><sup>52</sup></a> </p><p>Some vertical microcode is just the assembly language of a simple conventional computer that is emulating a more complex computer. Some processors, such as <a href="/facts/DEC_Alpha/4eN7LuXG">DEC Alpha</a> processors and the CMOS microprocessors on later IBM mainframes <a href="/facts/System%2f390/lzkp2UE5">System/390</a> and <a href="/facts/Z%2fArchitecture/FcKYkGn9">z/Architecture</a>, use machine code, running in a special mode that gives it access to special instructions, special registers, and other hardware resources unavailable to regular machine code, to implement some instructions and other functions,<a class="footnote-ref" id="fnref:53" href="#fn:53"><sup>53</sup></a><a class="footnote-ref" id="fnref:54" href="#fn:54"><sup>54</sup></a> such as page table walks on Alpha processors.<a class="footnote-ref" id="fnref:55" href="#fn:55"><sup>55</sup></a> This is called <a href="/facts/PALcode/7EqvwKYF">PALcode</a> on Alpha processors and <a href="/facts/Millicode/KwgVHFLW">millicode</a> on IBM mainframe processors. </p><p>Another form of vertical microcode has two fields: </p> <table><tbody><tr><td>Field select</td><td>Field value</td></tr></tbody></table> <p>The <i>field select</i> selects which part of the CPU will be controlled by this word of the control store. The <i>field value</i> controls that part of the CPU. With this type of microcode, a designer explicitly chooses to make a slower CPU to save money by reducing the unused bits in the control store; however, the reduced complexity may increase the CPU's clock frequency, which lessens the effect of an increased number of cycles per instruction. </p><p>As transistors grew cheaper, horizontal microcode came to dominate the design of CPUs using microcode, with vertical microcode being used less often. </p><p>When both vertical and horizontal microcode are used, the horizontal microcode may be referred to as <i>nanocode</i> or <i>picocode</i>.<a class="footnote-ref" id="fnref:56" href="#fn:56"><sup>56</sup></a> </p> <h2 id="writable-control-store">Writable control store</h2> <p class="note">Main article: <a href="/facts/Writable_control_store/Ts50verp">Writable control store</a></p> <p>A few computers were built using <i>writable microcode</i>. In this design, rather than storing the microcode in ROM or hard-wired logic, the microcode is stored in a RAM called a <i>writable control store</i> or <i>WCS</i>. Such a computer is sometimes called a <i>writable instruction set computer</i> (WISC).<a class="footnote-ref" id="fnref:57" href="#fn:57"><sup>57</sup></a> </p><p>Many experimental prototype computers use writable control stores; there are also commercial machines that use writable microcode, such as the <a href="/facts/Burroughs_Small_Systems/80aExR2b">Burroughs Small Systems</a>, early <a href="/facts/Xerox_PARC/fh2Su0k9">Xerox</a> workstations, the <a href="/facts/Digital_Equipment_Corporation/ztxs6keA">DEC</a> <a href="/facts/VAX/N3r13IHH">VAX</a> 8800 (<i>Nautilus</i>) family, the <a href="/facts/Symbolics/U8cJjbwb">Symbolics</a> L- and G-machines, a number of IBM System/360 and <a href="/facts/System%2f370/TRo1jaFw">System/370</a> implementations, some DEC <a href="/facts/PDP-10/zlfam4wk">PDP-10</a> machines,<a class="footnote-ref" id="fnref:58" href="#fn:58"><sup>58</sup></a> and the <a href="/facts/Data_General_Eclipse_MV%2f8000/RQsQBvPj">Data General Eclipse MV/8000</a>.<a class="footnote-ref" id="fnref:59" href="#fn:59"><sup>59</sup></a> </p><p>The IBM System/370 includes a facility called <i>Initial-Microprogram Load</i> (<i>IML</i> or <i>IMPL</i>)<a class="footnote-ref" id="fnref:60" href="#fn:60"><sup>60</sup></a> that can be invoked from the console, as part of <i><a href="/facts/Power-on_reset/B0Lh220y">power-on reset</a></i> (<i>POR</i>) or from another processor in a <a href="/facts/Tightly_coupled_system/aDCfehDQ">tightly coupled</a> <a href="/facts/Multiprocessor/aDCfehDQ">multiprocessor</a> complex. </p><p>Some commercial machines, for example IBM 360/85,<a class="footnote-ref" id="fnref:61" href="#fn:61"><sup>61</sup></a><a class="footnote-ref" id="fnref:62" href="#fn:62"><sup>62</sup></a> have both a read-only storage and a writable control store for microcode. </p><p>WCS offers several advantages including the ease of patching the microprogram and, for certain hardware generations, faster access than ROMs can provide. User-programmable WCS allows the user to optimize the machine for specific purposes. </p><p>Starting with the <a href="/facts/Pentium_Pro/mTAN64fo">Pentium Pro</a> in 1995, several <a href="/facts/X86/Kypq5fgu">x86</a> CPUs have writable <a href="/facts/Intel_Microcode/ezdcpMT2">Intel Microcode</a>.<a class="footnote-ref" id="fnref:63" href="#fn:63"><sup>63</sup></a><a class="footnote-ref" id="fnref:64" href="#fn:64"><sup>64</sup></a> This, for example, has allowed bugs in the <a href="/facts/Intel_Core_2/9gJP9o8p">Intel Core 2</a> and Intel <a href="/facts/Xeon/j1M8Hp6D">Xeon</a> microcodes to be fixed by patching their microprograms, rather than requiring the entire chips to be replaced. A second prominent example is the set of microcode patches that Intel offered for some of their processor architectures of up to 10 years in age, in a bid to counter the security vulnerabilities discovered in their designs – <a href="/facts/Spectre_(security_vulnerability)/1PBIla24">Spectre</a> and <a href="/facts/Meltdown_(security_vulnerability)/KVRY83cy">Meltdown</a> – which went public at the start of 2018.<a class="footnote-ref" id="fnref:65" href="#fn:65"><sup>65</sup></a><a class="footnote-ref" id="fnref:66" href="#fn:66"><sup>66</sup></a> A microcode update can be installed by Linux,<a class="footnote-ref" id="fnref:67" href="#fn:67"><sup>67</sup></a> <a href="/facts/FreeBSD/RKsFTm7F">FreeBSD</a>,<a class="footnote-ref" id="fnref:68" href="#fn:68"><sup>68</sup></a> Microsoft Windows,<a class="footnote-ref" id="fnref:69" href="#fn:69"><sup>69</sup></a> or the motherboard BIOS.<a class="footnote-ref" id="fnref:70" href="#fn:70"><sup>70</sup></a> </p><p>Some machines offer user-programmable writable control stores as an option, including the <a href="/facts/HP_2100/rdTIPT3h">HP 2100</a>, DEC <a href="/facts/PDP-11/9HkGUzFn">PDP-11/60</a>, <a href="/facts/TI-990/n94FdfMU">TI-990</a>/12,<a class="footnote-ref" id="fnref:71" href="#fn:71"><sup>71</sup></a><a class="footnote-ref" id="fnref:72" href="#fn:72"><sup>72</sup></a> and <a href="/facts/Varian_Data_Machines/RuaKsUwQ">Varian Data Machines</a> V-70 series <a href="/facts/Minicomputer/g8hvpQxe">minicomputers</a>. WCS options extended down to microprocessors too. The <a href="/facts/PDP-11/9HkGUzFn">DEC LSI-11</a> has an option to allow programming of the internal 8-bit micromachine to create application-specific extensions to the instruction set.<a class="footnote-ref" id="fnref:73" href="#fn:73"><sup>73</sup></a> </p> <h2 id="comparison-to-vliw-and-risc">Comparison to VLIW and RISC</h2> <p>The design trend toward heavily microcoded processors with complex instructions began in the early 1960s and continued until roughly the mid-1980s. At that point the <a href="/facts/RISC/aQbGM62p">RISC</a> design philosophy started becoming more prominent. </p><p>A CPU that uses microcode generally takes several clock cycles to execute a single instruction, one clock cycle for each step in the microprogram for that instruction. Some <a href="/facts/Complex_instruction_set_computer/Ucvyh2xq">CISC</a> processors include instructions that can take a very long time to execute. Such variations interfere with both <a href="/facts/Interrupt_latency/nu1RWx2F">interrupt latency</a> and, what is far more important in modern systems, <a href="/facts/Instruction_pipelining/3zy6CcX1">pipelining</a>. </p><p>When designing a new processor, a <a href="/facts/Hardwired_control/8QRX3lwf">hardwired control</a> RISC has the following advantages over microcoded CISC: </p> <ul><li>Programming has largely moved away from assembly level, so it's no longer worthwhile to provide complex instructions for productivity reasons.</li> <li>Simpler instruction sets allow direct execution by hardware, avoiding the performance penalty of microcoded execution.</li> <li>Analysis shows complex instructions are rarely used, hence the machine resources devoted to them are largely wasted.</li> <li>The machine resources devoted to rarely used complex instructions are better used for expediting performance of simpler, commonly used instructions.</li> <li>Complex microcoded instructions may require many clock cycles that vary, and are difficult to <a href="/facts/Pipeline_(computing)/xmHjrPMP">pipeline</a> for increased performance.</li></ul> <p>There are counterpoints as well: </p> <ul><li>The complex instructions in heavily microcoded implementations may not take much extra machine resources, except for microcode space. For example, the same ALU is often used to calculate an effective address and to compute the result from the operands, e.g., the original <a href="/facts/Z80/Jeqe2h55">Z80</a>, <a href="/facts/8086/sS9dlSdK">8086</a>, and others.</li> <li>The simpler non-RISC instructions (i.e., involving direct memory <a href="/facts/Operand/HSuUzrKz">operands</a>) are frequently used by modern compilers. Even immediate to stack (i.e., memory result) arithmetic operations are commonly employed. Although such memory operations, often with varying length encodings, are more difficult to pipeline, it is still fully feasible to do so - clearly exemplified by the <a href="/facts/I486/2zfEAXAw">i486</a>, <a href="/facts/AMD_K5/IPMKlDsR">AMD K5</a>, <a href="/facts/Cyrix_6x86/q43nNY14">Cyrix 6x86</a>, <a href="/facts/Motorola_68040/G12gptjt">Motorola 68040</a>, etc.</li> <li>Non-RISC instructions inherently perform more work per instruction (on average), and are also normally highly encoded, so they enable smaller overall size of the same program, and thus better use of limited cache memories.</li></ul> <p>Many RISC and <a href="/facts/Very_long_instruction_word/WJuzewyR">VLIW</a> processors are designed to execute every instruction (as long as it is in the cache) in a single cycle. This is very similar to the way CPUs with microcode execute one microinstruction per cycle. VLIW processors have instructions that behave similarly to very wide horizontal microcode, although typically without such fine-grained control over the hardware as provided by microcode. RISC instructions are sometimes similar to the narrow vertical microcode. </p><p>Microcode has been popular in application-specific processors such as <a href="/facts/Network_processor/SW5Lv8UM">network processors</a>, <a href="/facts/Digital_signal_processor/YuBXweos">digital signal processors</a>, <a href="/facts/Channel_I%2fO/vDBtN2wQ">channel controllers</a>, <a href="/facts/Disk_controller/dfRSYlMq">disk controllers</a>, <a href="/facts/Network_interface_controller/wyf5FR29">network interface controllers</a>, <a href="/facts/Flash_memory_controller/0LhGLTzj">flash memory controllers</a>, <a href="/facts/Graphics_processing_unit/PTK1RQVp">graphics processing units</a>, and in other hardware. </p> <h2 id="micro-operations">Micro-operations</h2> <p>Modern CISC implementations, such as the <a href="/facts/X86/Kypq5fgu">x86</a> family starting with the <a href="/facts/NexGen/7WWCsBnP">NexGen</a> Nx586, Intel <a href="/facts/Pentium_Pro/mTAN64fo">Pentium Pro</a>, and <a href="/facts/AMD_K5/IPMKlDsR">AMD K5</a>, decode instructions into dynamically buffered <a href="/facts/Micro-operation/9naSl6e9">micro-operations</a> with an instruction encoding similar to RISC or traditional microcode. A hardwired instruction decode unit directly emits microoperations for common x86 instructions, but falls back to a more traditional microcode ROM containing microoperations for more complex or rarely used instructions.<a class="footnote-ref" id="fnref:74" href="#fn:74"><sup>74</sup></a> </p><p>For example, an x86 might look up microoperations from microcode to handle complex multistep operations such as loop or string instructions, <a href="/facts/Floating-point_unit/XWTW2AbF">floating-point unit</a> <a href="/facts/Transcendental_function/yMkeq4Eo">transcendental functions</a> or unusual values such as <a href="/facts/Denormal_number/6qB24xrS">denormal numbers</a>, and special-purpose instructions such as <a href="/facts/CPUID/BdbdpdgB">CPUID</a>. </p> <h2 id="see-also">See also</h2> <ul> <li>Electronics portal</li></ul> <ul><li><a href="/facts/Address_generation_unit/KC7YYg8n">Address generation unit</a> (AGU)</li> <li><a href="/facts/CPU_design/HeNbj78g">CPU design</a></li> <li><a href="/facts/Finite-state_machine/GMusWd0a">Finite-state machine</a> (FSM)</li> <li><a href="/facts/Firmware/62UVKIUK">Firmware</a></li> <li><a href="/facts/Floating-point_unit/XWTW2AbF">Floating-point unit</a> (FPU)</li> <li><a href="/facts/Pentium_FDIV_bug/6mYzpbF1">Pentium FDIV bug</a></li> <li><a href="/facts/Instruction_pipeline/3zy6CcX1">Instruction pipeline</a></li> <li><a href="/facts/Microsequencer/7v30jEIr">Microsequencer</a></li> <li><a href="/facts/MikroSim/z2q5hdJt">MikroSim</a></li> <li><a href="/facts/Millicode/KwgVHFLW">Millicode</a></li> <li><a href="/facts/Superscalar/gPxRAb25">Superscalar</a></li></ul> <h2 id="notes">Notes</h2> <h2 id="further-reading">Further reading</h2> <ul><li>Smith, Richard E. (1988). <a href="http://doi.ieeecomputersociety.org/10.1109/MAHC.1988.10039">"A Historical Overview of Computer Architecture"</a>. <i><a href="/facts/Annals_of_the_History_of_Computing/SBnAgwVR">Annals of the History of Computing</a></i>. 10 (4): 277–303. <a href="/facts/Doi_(identifier)/muM9Etpq">doi</a>:<a href="https://doi.org/10.1109%2FMAHC.1988.10039">10.1109/MAHC.1988.10039</a>. <a href="/facts/S2CID_(identifier)/ldJsHa2Y">S2CID</a> <a href="https://api.semanticscholar.org/CorpusID:16405547">16405547</a>. Retrieved June 21, 2006.</li> <li>Smotherman, Mark (October 2022). <a href="https://people.computing.clemson.edu/~mark/uprog.html">"A Brief History of Microprogramming"</a>. Retrieved October 27, 2023.</li> <li><a href="/facts/Maurice_Wilkes/2RJ58EKc">Wilkes, M. V.</a> (1986). <a href="http://doi.ieeecomputersociety.org/10.1109/MAHC.1986.10035">"The Genesis of Microprogramming"</a>. <i>Annals of the History of Computing</i>. 8 (2): 116–126. <a href="/facts/Doi_(identifier)/muM9Etpq">doi</a>:<a href="https://doi.org/10.1109%2FMAHC.1986.10035">10.1109/MAHC.1986.10035</a>. <a href="/facts/S2CID_(identifier)/ldJsHa2Y">S2CID</a> <a href="https://api.semanticscholar.org/CorpusID:1978847">1978847</a>. Retrieved August 7, 2006.</li> <li><a href="/facts/Maurice_Wilkes/2RJ58EKc">Wilkes, M. V.</a>; <a href="/facts/John_Bentley_Stringer/EdMlAA3r">Stringer, J. B.</a> (April 1953). <a href="http://research.microsoft.com/~gbell/Computer_Structures_Principles_and_Examples/csp0174.htm">"Microprogramming and the Design of the Control Circuits in an Electronic Digital Computer"</a>. <i><a href="/facts/Mathematical_Proceedings_of_the_Cambridge_Philosophical_Society/KUUzcS7S">Mathematical Proceedings of the Cambridge Philosophical Society</a></i>. 49 (2): 230–238. <a href="/facts/Bibcode_(identifier)/9HtdQSGB">Bibcode</a>:<a href="https://ui.adsabs.harvard.edu/abs/1953PCPS...49..230W">1953PCPS...49..230W</a>. <a href="/facts/Doi_(identifier)/muM9Etpq">doi</a>:<a href="https://doi.org/10.1017%2FS0305004100028322">10.1017/S0305004100028322</a>. <a href="/facts/S2CID_(identifier)/ldJsHa2Y">S2CID</a> <a href="https://api.semanticscholar.org/CorpusID:62230627">62230627</a>. Retrieved August 23, 2006.</li> <li>Husson, S.S. (1970). <a href="https://archive.org/details/microprogramming00huss"><i>Microprogramming Principles and Practices</i></a>. Prentice-Hall. <a href="/facts/ISBN_(identifier)/15AdSPa9">ISBN</a> 0-13-581454-5.</li> <li>Tucker, S.G. (1967). <a href="http://domino.research.ibm.com/tchjr/journalindex.nsf/a3807c5b4823c53f85256561006324be/758c1e6a8a3e5d0285256bfa00685a2f?OpenDocument">"Microprogram control for SYSTEM/360"</a>. <i><a href="/facts/IBM_Systems_Journal/LswQR28R">IBM Systems Journal</a></i>. 6 (4): 222–241. <a href="/facts/Doi_(identifier)/muM9Etpq">doi</a>:<a href="https://doi.org/10.1147%2Fsj.64.0222">10.1147/sj.64.0222</a>.</li> <li>Shirriff, Ken (December 2022). <a href="https://www.righto.com/2022/11/how-8086-processors-microcode-engine.html">"How the 8086 processor's microcode engine works"</a>.</li></ul> <h2 id="external-links">External links</h2> Look up <i>microcode</i> in Wiktionary, the free dictionary. <ul><li><a href="http://c2.com/cgi/wiki?WritableInstructionSetComputer">Writable Instruction Set Computer</a></li> <li><a href="http://www.research.ibm.com/journal/rd/102/ibmrd1002F.pdf">Capacitor Read-only Store</a></li> <li><a href="https://web.archive.org/web/20050124004424/http://www-03.ibm.com/ibm/history/exhibits/attic3/attic3_016.html">Transformer Read-only Store</a></li> <li><a href="http://people.cs.clemson.edu/~mark/uprog.html">A Brief History of Microprogramming</a></li> <li><a href="https://lists.debian.org/debian-user/2013/09/msg00126.html">Intel processor microcode security update</a> (fixes the issues when running 32-bit virtual machines in PAE mode)</li> <li><a href="https://web.archive.org/web/20150907195925/http://inertiawar.com/microcode/hawkes_intel_microcode.pdf">Notes on Intel Microcode Updates</a>, March 2013, by Ben Hawkes, archived from the original on September 7, 2015</li> <li><a href="https://web.archive.org/web/20030309102752/http://www.eetimes.com/news/97/963news/hole.html">Hole seen in Intel's bug-busting feature</a>, <i><a href="/facts/EE_Times/XsxJNfCw">EE Times</a></i>, 2002, by Alexander Wolfe, archived from the original on March 9, 2003</li> <li><a href="http://www.securiteam.com/securityreviews/5FP0M1PDFO.html">Opteron Exposed: Reverse Engineering AMD K8 Microcode Updates</a>, July 26, 2004</li> <li><a href="https://ieeexplore.ieee.org/document/8662722">WepSIM: An Online Interactive Educational Simulator Integrating Microdesign, Microprogramming, and Assembly Language Programming</a>, July 26, 2022</li></ul> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>Kent, Allen; Williams, James G. (April 5, 1993). Encyclopedia of Computer Science and Technology: Volume 28 - Supplement 13. New York: Marcel Dekker, Inc. ISBN 0-8247-2281-7. Archived from the original on November 20, 2016. Retrieved Jan 17, 2016. <a href="0-8247-2281-7" target="_blank">0-8247-2281-7</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>Fog, Agner (2017-05-02). The microarchitecture of Intel, AMD and VIA CPUs (PDF) (Report). Technical University of Denmark. Archived (PDF) from the original on 2017-03-28. Retrieved 2024-08-21. <a href="https://www.agner.org/optimize/microarchitecture.pdf" target="_blank">https://www.agner.org/optimize/microarchitecture.pdf</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li> <li id="fn:3"><p>"IBM pSeries Servers - Microcode Update for Ultrastar 73LZX (US73) 18/36 GB". IBM. Archived from the original on April 19, 2019. Retrieved January 22, 2015. <a href="https://web.archive.org/web/20190419105117/http://download.boulder.ibm.com/ibmdl/pub/software/server/firmware/73lzx.html" target="_blank">https://web.archive.org/web/20190419105117/http://download.boulder.ibm.com/ibmdl/pub/software/server/firmware/73lzx.html</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li> <li id="fn:4"><p>Both, David (23 July 2020). "The central processing unit (CPU): Its components and functionality". Red Hat. <a href="https://www.redhat.com/sysadmin/cpu-components-functionality" target="_blank">https://www.redhat.com/sysadmin/cpu-components-functionality</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li> <li id="fn:5"><p>Both, David (23 July 2020). "The central processing unit (CPU): Its components and functionality". Red Hat. <a href="https://www.redhat.com/sysadmin/cpu-components-functionality" target="_blank">https://www.redhat.com/sysadmin/cpu-components-functionality</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></p></li> <li id="fn:6"><p>Pickens, John. "NMOS 6502 Opcodes". 6502.org. <a href="http://www.6502.org/tutorials/6502opcodes.html" target="_blank">http://www.6502.org/tutorials/6502opcodes.html</a> <a href="#fnref:6" class="footnote-back-ref">↩</a></p></li> <li id="fn:7"><p>Shirriff, Ken. "How the 8086 processor's microcode engine works". Ken Shirriff's blog. <a href="http://www.righto.com/2022/11/how-8086-processors-microcode-engine.html#:~:text=In%201951%2C%20Maurice%20Wilkes%20came,memory%20called%20a%20control%20store." target="_blank">http://www.righto.com/2022/11/how-8086-processors-microcode-engine.html#:~:text=In%201951%2C%20Maurice%20Wilkes%20came,memory%20called%20a%20control%20store.</a> <a href="#fnref:7" class="footnote-back-ref">↩</a></p></li> <li id="fn:8"><p>"ISO/IEC/IEEE 24765:2017(en) Systems and software engineering — Vocabulary". www.iso.org. Retrieved 2024-06-23. <a href="https://www.iso.org/obp/ui/#iso:std:iso-iec-ieee:24765:ed-2:v1:en" target="_blank">https://www.iso.org/obp/ui/#iso:std:iso-iec-ieee:24765:ed-2:v1:en</a> <a href="#fnref:8" class="footnote-back-ref">↩</a></p></li> <li id="fn:9"><p>VAX 9000 System Technical Description (PDF). Digital Equipment Corporation. May 1990. pp. 3-5 – 3-32. EK-KA90S-TD-001. <a href="http://www.bitsavers.org/pdf/dec/vax/9000/EK-KA90S-TD-001_VAX_9000_System_Technical_Description_May90.pdf" target="_blank">http://www.bitsavers.org/pdf/dec/vax/9000/EK-KA90S-TD-001_VAX_9000_System_Technical_Description_May90.pdf</a> <a href="#fnref:9" class="footnote-back-ref">↩</a></p></li> <li id="fn:10"><p>VAX 8800 System Technical Description Volume 2 (PDF). Digital Equipment Corporation. July 1986. EK-KA882-TD-PRE. <a href="http://bitsavers.org/pdf/dec/vax/8800/EK-KA882_8800sysTech2_Jul86.pdf" target="_blank">http://bitsavers.org/pdf/dec/vax/8800/EK-KA882_8800sysTech2_Jul86.pdf</a> <a href="#fnref:10" class="footnote-back-ref">↩</a></p></li> <li id="fn:11"><p>Manning, B.M.; Mitby, J.S; Nicholson, J.O. (November 1979). "Microprogrammed Processor Having PLA Control Store". IBM Technical Disclosure Bulletin. 22 (6). Archived from the original on 2012-10-01. Retrieved 2011-07-10. <a href="http://www.computerhistory.org/collections/accession/102660026" target="_blank">http://www.computerhistory.org/collections/accession/102660026</a> <a href="#fnref:11" class="footnote-back-ref">↩</a></p></li> <li id="fn:12"><p>Often denoted a ROM/PLA control store in the context of usage in a CPU; Supnik, Bob (24 February 2008). "J-11: DEC's fourth and last PDP-11 microprocessor design ... features ... ROM/PLA control store". Archived from the original on 2011-07-09. Retrieved 2011-07-10. <a href="http://simh.trailing-edge.com/semi/j11.html" target="_blank">http://simh.trailing-edge.com/semi/j11.html</a> <a href="#fnref:12" class="footnote-back-ref">↩</a></p></li> <li id="fn:13"><p>"6502 Images". Archived from the original on March 4, 2016. Retrieved January 22, 2015. <a href="http://www.visual6502.org/images/6502/" target="_blank">http://www.visual6502.org/images/6502/</a> <a href="#fnref:13" class="footnote-back-ref">↩</a></p></li> <li id="fn:14"><p>IBM System/360 Model 50 Functional Characteristics (PDF). IBM. 1967. p. 7. A22-6898-1. Retrieved October 29, 2021. <a href="http://bitsavers.org/pdf/ibm/360/functional_characteristics/A22-6898-1_360-50_funcChar_1967.pdf" target="_blank">http://bitsavers.org/pdf/ibm/360/functional_characteristics/A22-6898-1_360-50_funcChar_1967.pdf</a> <a href="#fnref:14" class="footnote-back-ref">↩</a></p></li> <li id="fn:15"><p>Everett, R.R.; Swain, F.E. (1947). Whirlwind I Computer Block Diagrams (PDF) (Technical report). MIT Servomechanisms Laboratory. R-127. Archived from the original (PDF) on June 17, 2012. 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