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List of MIPS architecture processors
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<h2 id="mips-computer-systemsmips-technologies">MIPS Computer Systems/MIPS Technologies</h2> <table><tbody><tr><th>MIPS version</th><th>Processor</th><th>Year</th><th>Process (nm)</th><th>Frequency (MHz)</th><th>Transistors (millions)</th><th>Die area (mm2)</th><th>Pin count</th><th>Power (W)</th><th>Voltage (V)</th><th>D. cache (KB)</th><th>I. cache (KB)</th><th><a href="/facts/Memory_management_unit/tJQtAQzI">MMU</a></th><th>L2 cache</th><th>L3 cache</th><th>Features</th></tr><tr><th rowspan="2"><a href="/facts/MIPS_I/efV4KgK4">MIPS I</a></th><td><a href="/facts/R2000_(microprocessor)/wGtpAxzS">R2000</a></td><td>1985</td><td>2000</td><td>8 to 16.67</td><td>0.11</td><td>80</td><td></td><td></td><td></td><td>64 external</td><td>64 external</td><td></td><td><i>none</i></td><td><i>none</i></td><td>5 stage pipelines, FPU: 2010</td></tr><tr><td><a href="/facts/R3000/pKuMSw50">R3000</a></td><td>1988</td><td>1200</td><td>12 to 40</td><td>0.11</td><td>40</td><td>145, 172</td><td>4</td><td></td><td>32-256 external</td><td>32-256 external</td><td></td><td>0-1 MB external</td><td><i>none</i></td><td>same as R2000; FPU: 3010</td></tr><tr><th rowspan="1"><a href="/facts/MIPS_II/efV4KgK4">MIPS II</a></th><td><a href="/facts/R6000/g4gMatpk">R6000</a></td><td>1990</td><td></td><td>60 to 66</td><td></td><td></td><td></td><td></td><td></td><td>external</td><td>external</td><td></td><td><i>none</i></td><td><i>none</i></td><td>32-bit register size, 36-bit physical address, FPU</td></tr><tr><th rowspan="8"><a href="/facts/MIPS_III/efV4KgK4">MIPS III</a></th><td><a href="/facts/R4000/1XxfW4gC">R4000</a></td><td>1991</td><td>800</td><td>100</td><td>1.35</td><td>213</td><td>179</td><td>15</td><td>5</td><td>8</td><td>8</td><td></td><td>128 KB to 4 MB external</td><td><i>none</i></td><td></td></tr><tr><td><a href="/facts/R4400/1XxfW4gC">R4400</a></td><td>1992</td><td>600</td><td>100 to 250</td><td>2.3</td><td>186</td><td>179</td><td>15</td><td>5, 3.3</td><td>16</td><td>16</td><td></td><td>128 KB to 4 MB external</td><td><i>none</i></td><td></td></tr><tr><td><a href="/facts/R4200/YQJ5jdI5">R4200</a></td><td>1993</td><td>600</td><td>80</td><td>1.3</td><td>81</td><td>179</td><td>1.8-2.0</td><td>3.3</td><td>8</td><td>16</td><td></td><td>128 KB to 4 MB external</td><td><i>none</i></td><td><a href="/facts/Scalar_processor/Rwma07cc">scalar</a> design with a five-stage <a href="/facts/Classic_RISC_pipeline/67UhbP04">classic RISC pipeline</a></td></tr><tr><td><a href="/facts/R4300i/YQJ5jdI5">R4300i</a></td><td>1995</td><td>350</td><td>100 / 133</td><td></td><td>45</td><td>120</td><td>2.2</td><td>3.3</td><td></td><td></td><td></td><td></td><td><i>none</i></td><td></td></tr><tr><td><a href="/facts/R4600/DVvLoKjW">R4600</a></td><td>1994</td><td>640</td><td>100 / 133</td><td>2.2</td><td>77</td><td>179</td><td>4.6</td><td>5</td><td>16</td><td>16</td><td></td><td>512 KB external</td><td><i>none</i></td><td></td></tr><tr><td><a href="/facts/R4650/DVvLoKjW">R4650</a></td><td>1994</td><td>640</td><td>133 / 180</td><td>2.2</td><td>77</td><td>179</td><td>4.6</td><td>5</td><td>16</td><td>16</td><td></td><td>512 KB external</td><td><i>none</i></td><td></td></tr><tr><td><a href="/facts/R4640/DVvLoKjW">R4640</a></td><td>1995</td><td>640</td><td></td><td></td><td></td><td>179</td><td></td><td></td><td></td><td></td><td></td><td></td><td><i>none</i></td><td></td></tr><tr><td><a href="/facts/R4700/DVvLoKjW">R4700</a></td><td>1996</td><td>500</td><td>100 to 200</td><td>2.2</td><td></td><td>179</td><td></td><td></td><td>16</td><td>16</td><td></td><td>External</td><td><i>none</i></td><td></td></tr><tr><th rowspan="11"><a href="/facts/MIPS_IV/efV4KgK4">MIPS IV</a></th><td><a href="/facts/R5000/oWIUcwX1">R5000</a></td><td>1996</td><td>350</td><td>150 to 200</td><td>3.7</td><td>84</td><td>223</td><td>10</td><td>3.3</td><td>32</td><td>32</td><td></td><td>1 MB external</td><td><i>none</i></td><td></td></tr><tr><td><a href="/facts/R5000/oWIUcwX1">RM7000</a></td><td>1998</td><td>250, 180, 130</td><td>250 to 600</td><td>18</td><td>91</td><td>304</td><td>10, 6, 3</td><td>3.3, 2.5, 1.5</td><td>16</td><td>16</td><td></td><td>256 KB internal</td><td>1 MB external</td><td></td></tr><tr><td><a href="/facts/R8000/unon78tr">R8000</a></td><td>1994</td><td>700</td><td>75 to 90</td><td>2.6</td><td>299</td><td>591</td><td>30</td><td>3.3</td><td>16</td><td>16</td><td></td><td>4 MB external</td><td><i>none</i></td><td><a href="/facts/Superscalar/gPxRAb25">superscalar</a>, up to 4 instructions per cycle</td></tr><tr><td><a href="/facts/R10000/3akwp9US">R10000</a></td><td>1996</td><td>350, 250</td><td>150 to 250</td><td>6.7</td><td>350</td><td>599</td><td>30</td><td>3.3</td><td>32</td><td>32</td><td></td><td>512 KB – 16 MB external</td><td><i>none</i></td><td></td></tr><tr><td><a href="/facts/R10000/3akwp9US">R12000</a></td><td>1998</td><td>350, 250</td><td>270 to 360</td><td>7.15</td><td>229</td><td>600</td><td>20</td><td>4</td><td>32</td><td>32</td><td></td><td>512 KB – 16 MB external</td><td><i>none</i></td><td>single-chip 4-issue superscalar</td></tr><tr><td><a href="/facts/R10000/3akwp9US">R12000A</a></td><td>2000</td><td>180</td><td>400</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td><i>none</i></td><td></td></tr><tr><td><a href="/facts/R10000/3akwp9US">R14000</a></td><td>2001</td><td>130</td><td>500</td><td>7.2</td><td>204</td><td>527</td><td>17</td><td></td><td>32</td><td>32</td><td></td><td>512 KB – 16 MB external</td><td><i>none</i></td><td></td></tr><tr><td><a href="/facts/R10000/3akwp9US">R14000A</a></td><td>2002</td><td>130</td><td>600</td><td></td><td></td><td></td><td>17</td><td></td><td>32</td><td>32</td><td></td><td></td><td><i>none</i></td><td></td></tr><tr><td><a href="/facts/R10000/3akwp9US">R16000</a></td><td>2003</td><td>110</td><td>700 to 1000</td><td></td><td></td><td></td><td>20</td><td></td><td>64</td><td>64</td><td></td><td>512 KB – 16 MB external</td><td><i>none</i></td><td></td></tr><tr><td><a href="/facts/R10000/3akwp9US">R16000A</a></td><td>2004</td><td>110</td><td>800 to 1000</td><td></td><td></td><td></td><td></td><td></td><td>64</td><td>64</td><td></td><td></td><td><i>none</i></td><td></td></tr><tr><td><a href="/facts/R10000/3akwp9US">R18000</a></td><td>2001</td><td>130</td><td></td><td></td><td></td><td></td><td></td><td>1.2</td><td>32</td><td>32</td><td></td><td>1 MB</td><td>0-64 MB external, on-chip tag</td><td>was planned, but not manufactured</td></tr><tr><th rowspan="2"><a href="/facts/MIPS_V/efV4KgK4">MIPS V</a></th><td>H1 "Beast"</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td><i>none</i></td><td>was planned, but not manufactured</td></tr><tr><td>H2 "Captain"</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td><i>none</i></td><td>was planned, but not manufactured</td></tr><tr><th rowspan="13"><a href="/facts/MIPS32/efV4KgK4">MIPS32</a></th><td>4K</td><td>1999</td><td>180</td><td>167</td><td></td><td>2.5</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td><i>none</i></td><td></td></tr><tr><td>4KE</td><td></td><td>90</td><td>420</td><td></td><td>1.2</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td><i>none</i></td><td></td></tr><tr><td>24K</td><td>2003</td><td>130, 65, 40</td><td>400 (130 nm) 750 (65 nm) 1468 (40 nm)</td><td></td><td>0.83</td><td></td><td></td><td></td><td>0 to 64</td><td>0 to 64</td><td></td><td>4–16 MB external</td><td><i>none</i></td><td></td></tr><tr><td>24KE</td><td>2003</td><td>130, 65, 40</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td><i>none</i></td><td></td></tr><tr><td>34K</td><td>2006</td><td>90, 65, 40</td><td>500 (90 nm) 1454 (40 nm)</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td><i>none</i></td><td></td></tr><tr><td>74K</td><td>2007</td><td>65</td><td>1110</td><td></td><td>2.5</td><td></td><td></td><td></td><td>0 to 64</td><td>0 to 64</td><td></td><td></td><td><i>none</i></td><td></td></tr><tr><td>1004K</td><td>2008</td><td>65</td><td>1100</td><td></td><td>4.7</td><td></td><td></td><td></td><td>8 to 64</td><td>8 to 64</td><td></td><td></td><td><i>none</i></td><td></td></tr><tr><td>M14K</td><td>2009</td><td>130</td><td>200</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td><i>none</i></td><td>MicroMIPS</td></tr><tr><td>1074K</td><td>2010</td><td>40</td><td>1500</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td><i>none</i></td><td></td></tr><tr><td>1074Kf</td><td>2010</td><td>40</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td><i>none</i></td><td>Floating point</td></tr><tr><td>microAptiv</td><td>2012</td><td>90, 65</td><td></td><td></td><td></td><td></td><td></td><td></td><td>8 to 64</td><td>8 to 64</td><td></td><td></td><td><i>none</i></td><td></td></tr><tr><td>interAptiv</td><td>2012</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td>4 to 64</td><td>4 to 64</td><td></td><td>up to 8 MB internal</td><td><i>none</i></td><td></td></tr><tr><td>proAptiv</td><td>2012</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td>32 or 64</td><td>32 or 64</td><td></td><td>up to 8 MB internal</td><td><i>none</i></td><td></td></tr><tr><th rowspan="2"><a href="/facts/MIPS64/efV4KgK4">MIPS64</a></th><td>5K</td><td>1999</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>20K</td><td>2000</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><th>MIPS version</th><th>Processor</th><th>Year</th><th>Process (nm)</th><th>Frequency (MHz)</th><th>Transistors (millions)</th><th>Die area (mm2)</th><th>Pin count</th><th>Power (W)</th><th>Voltage (V)</th><th>D. cache (KB)</th><th>I. cache (KB)</th><th><a href="/facts/Memory_management_unit/tJQtAQzI">MMU</a></th><th>L2 cache</th><th>L3 cache</th><th>Features</th></tr></tbody></table> <h2 id="imagination-technologies">Imagination Technologies</h2> <p><a href="/facts/MIPS_Technologies/eI0XPIYW">MIPS Technologies</a> was acquired 17 December 2012, by <a href="/facts/Imagination_Technologies/2nj1lCRC">Imagination Technologies</a>. Since then, the following processors have been introduced by Imagination Technologies. </p><p>Imagination Technologies sold MIPS processor rights to Tallwood MIPS Inc in 2017.<a class="footnote-ref" id="fnref:1" href="#fn:1"><sup>1</sup></a> MIPS Technologies was acquired by <a href="/facts/Wave_Computing/eI0XPIYW">Wave Computing</a> in 2018, where "MIPS operates as an IP licensing business unit".<a class="footnote-ref" id="fnref:2" href="#fn:2"><sup>2</sup></a><a class="footnote-ref" id="fnref:3" href="#fn:3"><sup>3</sup></a> </p><p>The Warrior P-Class CPU was announced on 14 October 2013.<a class="footnote-ref" id="fnref:4" href="#fn:4"><sup>4</sup></a> </p><p>The CPU IP cores comprising the MIPS Series5 ‘Warrior’ family are based on <a href="/facts/MIPS_architecture/efV4KgK4">MIPS32 release 5</a> and <a href="/facts/MIPS_architecture/efV4KgK4">MIPS64 release 6</a>, and will come in three classes of performance and features: </p> <ul><li>'Warrior M-class': entry-level MIPS cores for embedded and microcontroller applications, a progression from the popular microAptiv family</li> <li>'Warrior I-class': mid-range, feature-rich MIPS CPUs following on from the highly efficient interAptiv family. The I6400, with its 64-bit core, was launched September 2014.<a class="footnote-ref" id="fnref:5" href="#fn:5"><sup>5</sup></a></li> <li>'Warrior P-class': high-performance MIPS processors building on the proAptiv family</li></ul> <table><tbody><tr><th>MIPS version</th><th>level</th><th>Processor</th><th>Year</th><th>Process (nm)</th><th>Frequency (GHz)</th><th>Transistors (billions)</th><th>Die area (mm2)</th><th>Pin count</th><th>Power (W)</th><th>Voltage (V)</th><th>D. cache (KB)</th><th>I. cache (KB)</th><th><a href="/facts/Memory_management_unit/tJQtAQzI">MMU</a></th><th>L2 cache</th><th>L3 cache</th><th>Features</th></tr><tr><th rowspan="3"><a href="/facts/MIPS32/efV4KgK4">MIPS32</a> Release 5</th><td>Warrior-P</td><td>P5600</td><td>2013</td><td>?</td><td>1.0 to 2.0</td><td>?</td><td>?</td><td>?</td><td>?</td><td>?</td><td>32/64</td><td>32/64</td><td>TLb</td><td>Up to 8 MB external</td><td><i>none</i></td><td>VZ, MSA</td></tr><tr><td>Warrior-M</td><td>M5100</td><td>2014</td><td>65/28</td><td>0.1 to 0.497</td><td>?</td><td>0.04 to 0.77</td><td>?</td><td></td><td></td><td><i>none</i></td><td><i>none</i></td><td>FMT</td><td><i>none</i></td><td><i>none</i></td><td>VZ</td></tr><tr><td>Warrior-M</td><td>M5150</td><td>2014</td><td>65/28</td><td>0.372/0.576</td><td>?</td><td>0.89/0.26</td><td>?</td><td></td><td></td><td>up to 64</td><td>up to 64</td><td>TLB</td><td><i>none</i></td><td><i>none</i></td><td>VZ</td></tr><tr><th rowspan="4"><a href="/facts/MIPS64/efV4KgK4">MIPS64</a> Release 6</th><td>Warrior-P</td><td>P6600</td><td>2015</td><td>28</td><td>Up to 2.0</td><td>?</td><td>?</td><td>?</td><td>?</td><td>?</td><td>32/64</td><td>32/64</td><td>TLB</td><td>0.5 - 8 MB external</td><td><i>none</i></td><td>SMT, VZ</td></tr><tr><td>Warrior-I</td><td>I6400</td><td>2014</td><td>28</td><td>1.0</td><td>?</td><td>1/core</td><td>?</td><td>?</td><td>?</td><td>32/64</td><td>32/64</td><td>TLB</td><td>0.5 - 8 MB external</td><td><i>none</i></td><td>SMT, VZ</td></tr><tr><td>Warrior-M</td><td>M6200</td><td>2015</td><td>65/40/28</td><td>up to 0.750</td><td>?</td><td>0.19</td><td>?</td><td></td><td></td><td><i>none</i></td><td><i>none</i></td><td>FMT</td><td><i>none</i></td><td><i>none</i></td><td></td></tr><tr><td>Warrior-M</td><td>M6250</td><td>2015</td><td>65/40/28</td><td>up to 0.750</td><td>?</td><td>0.23</td><td>?</td><td></td><td></td><td>up to 64</td><td>up to 64</td><td>TLB</td><td><i>none</i></td><td><i>none</i></td><td>XPA</td></tr><tr><th>MIPS version</th><th>level</th><th>Processor</th><th>Year</th><th>Process (nm)</th><th>Frequency (GHz)</th><th>Transistors (billions)</th><th>Die area (mm2)</th><th>Pin count</th><th>Power (W)</th><th>Voltage (V)</th><th>D. cache (KB)</th><th>I. cache (KB)</th><th><a href="/facts/Memory_management_unit/tJQtAQzI">MMU</a></th><th>L2 cache</th><th>L3 cache</th><th>Features</th></tr></tbody></table> <h2 id="other-designers">Other designers</h2> <p>A number of companies licensed the MIPS architecture and developed their own processors. </p> <table><tbody><tr><th>MIPS version</th><th>Licensee</th><th>Processor</th><th>Features</th><th>Year</th><th>Process (nm)</th><th>Frequency (MHz)</th><th>Transistors (millions)</th><th>Die size (mm2)</th><th>Pin count</th><th>Power (W)</th><th>Voltage (V)</th><th>D. cache (KB)</th><th>I. cache (KB)</th><th><a href="/facts/Memory_management_unit/tJQtAQzI">MMU</a></th><th>L2 cache</th><th>L3 cache</th></tr><tr><th><a href="/facts/MIPS_I/efV4KgK4">MIPS I</a></th><td><a href="/facts/Lexra/MAw1STLE">Lexra</a></td><td>LX4080, LX4180, LX4280, LX5280, LX8000</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><th><a href="/facts/MIPS_II/efV4KgK4">MIPS II</a></th><td><a href="/facts/Scientific_Research_Institute_of_System_Development/xKUGNFMM">НИИСИ РАН</a></td><td><a href="/facts/KOMDIV-32/yjdd4c9B">KOMDIV-32</a></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><th rowspan="2"><a href="/facts/MIPS_III/efV4KgK4">MIPS III</a></th><td rowspan="1"><a href="/facts/Sony_Computer_Entertainment/tnH01NqQ">Sony Computer Entertainment</a> + <a href="/facts/Toshiba/QHRaw8Tr">Toshiba</a></td><td><a href="/facts/Emotion_Engine/y9npRux0">Emotion Engine</a></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>НИИСИ РАН</td><td><a href="/facts/KOMDIV-64/yagpCdQ1">KOMDIV-64</a></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><th rowspan="8"><a href="/facts/MIPS32/efV4KgK4">MIPS32</a></th><td rowspan="1">Alchemy Semiconductor</td><td><a href="/facts/Alchemy_(processor)/JNcE8qpM">Au1</a></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td rowspan="5"><a href="/facts/Broadcom/pbh0q7ht">Broadcom</a></td><td>BMIPS3000</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>BMIPS4000</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>BMIPS5000</td><td></td><td></td><td></td><td>1300</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>BCM53001</td><td></td><td></td><td>65</td><td>400</td><td></td><td></td><td></td><td></td><td></td><td>32</td><td>32</td><td></td><td></td><td></td></tr><tr><td>BCM1255</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td rowspan="2"><a href="/facts/Ingenic_Semiconductor/c71BoAld">Ingenic Semiconductor</a></td><td><a href="/facts/Ingenic_Semiconductor/c71BoAld">XBurst 1</a></td><td>single issue, 8-stage pipeline</td><td>2005</td><td>180, 130, 64, 40</td><td>240</td><td></td><td></td><td></td><td>0.15</td><td>1.8</td><td>16</td><td>16</td><td>yes</td><td>none</td><td>none</td></tr><tr><td><a href="/facts/Ingenic_Semiconductor/c71BoAld">XBurst 2</a></td><td>dual-issue/dual-threaded</td><td>2013</td><td>40</td><td>1200</td><td></td><td></td><td></td><td>0.15</td><td>1.8</td><td>32</td><td>32</td><td>yes</td><td>512</td><td>none</td></tr><tr><th rowspan="13"><a href="/facts/MIPS64/efV4KgK4">MIPS64</a></th><td rowspan="1"><a href="/facts/SiByte/8V4na6a7">SiByte</a></td><td>SB1</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td rowspan="2"><a href="/facts/Broadcom/pbh0q7ht">Broadcom</a></td><td>BCM1125H</td><td></td><td></td><td></td><td>400-800</td><td></td><td></td><td></td><td>4w @ 400 MHz</td><td></td><td>32</td><td>32</td><td>yes</td><td>256 KB</td><td></td></tr><tr><td>BCM1255</td><td>Dual-core, DDR2, 4× Gigabit LAN</td><td></td><td></td><td>800-1200</td><td></td><td></td><td></td><td>13 W @ 1 GHz</td><td></td><td>32</td><td>32</td><td>yes</td><td>512 KB</td><td></td></tr><tr><td rowspan="4"><a href="/facts/Cavium/JYaGIL4Y">Cavium</a></td><td>Octeon: CN30xx, CN31xx, CN36xx, CN38xx</td><td></td><td>2006</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>Octeon Plus: CN5xxx</td><td></td><td>2007</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>Octeon II: CN6xxx</td><td></td><td>2009</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>Octeon III: CN7xxx</td><td></td><td>2012</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td rowspan="4"><a href="/facts/NEC/YnlUsMBA">NEC</a></td><td>VR4305</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>VR4310</td><td></td><td>1997<a class="footnote-ref" id="fnref:6" href="#fn:6"><sup>6</sup></a></td><td>250</td><td>100,133,167</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>VR5432</td><td></td><td>1998</td><td></td><td>167</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>VR5464</td><td></td><td>1998</td><td></td><td>200-250</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td rowspan="2"><a href="/facts/NXP_Semiconductors/naAqdtWq">NXP Semiconductors</a></td><td>??</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>??</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td rowspan="2"><a href="/facts/Chinese_Academy_of_Sciences/zzHb3yVm">CAS: ICT</a></td><td><a href="/facts/Loongson/6AhDhaeU">none yet</a></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>??</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><th>MIPS version</th><th>Licensee</th><th>Processor</th><th>Features</th><th>Year</th><th>Process (nm)</th><th>Frequency (MHz)</th><th>Transistors (millions)</th><th>Die size (mm2)</th><th>Pin count</th><th>Power (W)</th><th>Voltage (V)</th><th>D. cache (KB)</th><th>I. cache (KB)</th><th><a href="/facts/Memory_management_unit/tJQtAQzI">MMU</a></th><th>L2 cache</th><th>L3 cache</th></tr></tbody></table> <h2 id="other">Other</h2> <ul><li><a href="/facts/PhysX_P1/cay9UPA0">PhysX P1</a> - A multi-core <a href="/facts/Physics_processing_unit/cay9UPA0">physics processing unit</a> that contains MIPS cores</li></ul> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>"Completion of sale of MIPS - Imagination". 25 October 2017. <a href="https://www.imaginationtech.com/news/press-release/completion-of-sale-of-mips/" target="_blank">https://www.imaginationtech.com/news/press-release/completion-of-sale-of-mips/</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>"Wave Computing and MIPS Technologies Reach Agreement to Exit Bankruptcy". <a href="https://www.prnewswire.com/news-releases/wave-computing-and-mips-technologies-reach-agreement-to-exit-bankruptcy-301198786.html" target="_blank">https://www.prnewswire.com/news-releases/wave-computing-and-mips-technologies-reach-agreement-to-exit-bankruptcy-301198786.html</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li> <li id="fn:3"><p>"About – MIPS". Retrieved 2019-11-06. <a href="https://www.mips.com/about/" target="_blank">https://www.mips.com/about/</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li> <li id="fn:4"><p>"Imagination reveals first MIPS 'Warrior P-class' CPU core". 2013-10-14. Retrieved 2013-10-28. <a href="http://www.imgtec.com/News/Release/index.asp?NewsID=804" target="_blank">http://www.imgtec.com/News/Release/index.asp?NewsID=804</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li> <li id="fn:5"><p>"MIPS reborn with 64-bit core launch". <a href="http://www.v3.co.uk/v3-uk/news/2363163/mips-architecture-reborn-with-64-bit-mips-i6400-targeting-mobile-devices-to-servers" target="_blank">http://www.v3.co.uk/v3-uk/news/2363163/mips-architecture-reborn-with-64-bit-mips-i6400-targeting-mobile-devices-to-servers</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></p></li> <li id="fn:6"><p>Shandor, John (3 October 1997). "Product Watch: IBM Intros Token Ring Plans. NEC Unveils VR4310 Processor. DEC Intros PCI Bridge Chips". HPCwire. <a href="https://www.hpcwire.com/1997/10/03/product-watch-ibm-intros-token-ring-plans-nec-unveils-vr4310-processor-dec-intros-pci-bridge-chips/" target="_blank">https://www.hpcwire.com/1997/10/03/product-watch-ibm-intros-token-ring-plans-nec-unveils-vr4310-processor-dec-intros-pci-bridge-chips/</a> <a href="#fnref:6" class="footnote-back-ref">↩</a></p></li> </ol>