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Motorola 6845
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<h2 id="design">Design</h2> <p>Originally designed by <a href="/facts/Hitachi%2c_Ltd./KeK38e82">Hitachi</a> as the HD46505,<a class="footnote-ref" id="fnref:5" href="#fn:5"><sup>5</sup></a> Hitachi-built versions are in a wide variety of Japanese computers, from Sony, Sharp, Panasonic, and Casio. Cloned later as MB89321A by Fujitsu.<a class="footnote-ref" id="fnref:6" href="#fn:6"><sup>6</sup></a> It is also known as the 6845 CRTC or the CRTC6845, meaning "<a href="/facts/Cathode-ray_tube/8NVGx5C7">cathode-ray tube</a> controller". This version was used on the <a href="/facts/Apricot_PC/2xJ2Y7EC">Apricot PC</a> and <a href="/facts/Victor_9000/zTBLnFTX">Victor 9000</a> to provide a 800x400 resolution monochrome display. </p><p>A common clone of this CRT controller is the <a href="/facts/United_Microelectronics_Corporation/yWTN3oDV">United Microelectronics Corporation</a> (UMC) UM6845E CRT controller. During the time of <a href="/facts/Coordinating_Committee_for_Multilateral_Export_Controls/qHYhGQX7">cold war technology embargoes</a>, the 6845 was cloned in Bulgaria under the designation CM607. The 6845 was very similar and related to the later 6545 manufactured by MOS Technology (Commodore Semiconductor Group) and Rockwell (in two versions). </p><p><a class="footnote-ref" id="fnref:7" href="#fn:7"><sup>7</sup></a> </p> <h2 id="overview">Overview</h2> <p>The chip generates the signals necessary to interface with a raster <a href="/facts/Computer_monitor/NRaTDFHc">display</a> but does not generate the actual <a href="/facts/Pixel/UzwBvXBV">pixels</a>, though it does contribute cursor and video-blanking information to the pixel video (intensity) signals. It is used to produce correctly timed horizontal and vertical sync and provide the address in memory from which the next pixel or set of pixels should be read. The process of reading that value, converting it into pixels, and sending it to a <a href="/facts/Cathode-ray_tube/8NVGx5C7">CRT</a> is left to other circuits. Because of this, systems using the 6845 may have very different numbers and values of colors, or may not support color at all.<a class="footnote-ref" id="fnref:8" href="#fn:8"><sup>8</sup></a> </p><p><a href="/facts/Interlaced_video/YBk246TF">Interlaced</a> and non-interlaced output modes are supported, as is a hardware text cursor. The sync generation includes generation of horizontal and vertical video blanking signals, which are used to condition the external pixel generation circuits. Also, an internal latch is provided which when triggered will duplicate and retain a copy of the video address so that it can later be read back by the CPU. This is useful for <a href="/facts/Light_pen/NkqLws4S">light pens</a> and <a href="/facts/Light_gun/KMuLDXhd">light guns</a> which can function by sending a pulse to the 6845 when the electron beam passes, allowing a running program to read back the location that was pointed at. Because of this feature, most computer video adapters using a 6845 included a light pen interface, though it was usually an internal connector on the board itself, not on the outside of the computer, and it was usually undocumented in the user manual. </p><p>Because all aspects of video timing are programmable, a single machine can switch between 50Hz and 60Hz timings in software (or indeed any other refresh rates within the limits of the chip). The 6845 can be used to drive <a href="/facts/Computer_monitor/NRaTDFHc">monitors</a> or any other raster display. </p> <h2 id="internals">Internals</h2> <p>The chip has a total of 18 <a href="/facts/8-bit/2CkhLNoH">8-bit</a> <a href="/facts/Hardware_register/V1roVh0p">registers</a> controlling all aspects of video timings. Only two addresses are exposed to external components - one to select which internal register is to be read or written to and another to access that register.<a class="footnote-ref" id="fnref:9" href="#fn:9"><sup>9</sup></a> </p> <table><tbody><tr><th>N. º of<p>register</p></th><th>Function</th></tr><tr><td>0</td><td>Total horizontal, in number of characters</td></tr><tr><td>1</td><td>Number of horizontal characters displayed per row</td></tr><tr><td>2</td><td>Horizontal sync position</td></tr><tr><td>3</td><td>Horizontal sync width, in number of characters</td></tr><tr><td>4</td><td>Total vertical, in character rows</td></tr><tr><td>5</td><td>Vertical total adjustment, in number of scan lines</td></tr><tr><td>6</td><td>Number of rows displayed (vertically)</td></tr><tr><td>7</td><td>Vertical sync position, in # rows of characters</td></tr><tr><td>8</td><td>Interlace mode</td></tr><tr><td>9</td><td>Character height, in scan lines (minus one)</td></tr><tr><td>10</td><td>Start of cursor, in scan line</td></tr><tr><td>11</td><td>End of cursor, in scan line</td></tr><tr><td>12</td><td>Screen Start Address (High)</td></tr><tr><td>13</td><td>Screen Start Address (Low)</td></tr><tr><td>14</td><td>Cursor Address (High)</td></tr><tr><td>15</td><td>Cursor Address (Low)</td></tr><tr><td>16</td><td>Light Pen Address (High)</td></tr><tr><td>17</td><td>Light Pen Address (Low)</td></tr></tbody></table> <p>The 6845 is intended for character based displays. Every address it generates is composed of two parts - a 14 bit character address and a 5 bit row address. The character address increases linearly. When the chip signals horizontal sync it increases the row address. If the row address does not equal the programmatically set number of rows per character, then the character address is reset to the value it had at the beginning of the scan line that was just completed. Otherwise the row address is reset to zero and the memory address continues increasing linearly. This causes the same sequence of character values to be re-read from the memory for each raster line of each character row, before the 6845 advances the memory address to the next character row and repeats the same pattern. </p><p>If the character address is used to look up a character reference in <a href="/facts/Random-access_memory/DuD4bxh6">RAM</a> and the row address to index a table of character graphics in <a href="/facts/Read-only_memory/P9QMuDLH">ROM</a> an ordinary <a href="/facts/Text_mode/641fGn4S">text mode</a> display is constructed. The character reference read from memory must be combined with the row address to form the address for the character graphics ROM, with the character reference selecting a set of scan line patterns that forms one character and the row address indexing into that set to select one scan line. In other words, the ROM address is split into two parts in order to use the ROM as a two-dimensional array: the first dimension selects a character, and the second selects a row of that character's graphic pattern. </p><p>However, the 6845 left to the designer the freedom to route the bits of the memory and row addresses to video RAM as they saw fit. For this reason the word addressed by the 6845 does not have to equal one pixel or one character. In CGA alphanumeric (text) mode, there are two bytes per character, accessed sequentially by the 6845—the first byte is a character code byte and the second byte is a character attribute byte—and the board uses the contents of the bytes, together with the row address, to read font data from ROM and generate the pixels. </p><p>Different routing of the bits, omitting the character ROM, could be used to emulate a frame buffer. Due to its 128 line limitation, the 6845 is not able to provide linear large linear frame buffers. A solution was to combine row address and character address to provide linear scanlines within a non-linear buffer. This has the advantages of easier programming for non-character display and easy smooth horizontal scrolling but can impede smooth vertical scrolling. For example the IBM CGA graphics mode uses a word size of one byte, and each word represents four or eight pixels (in the medium- or high-resolution graphics modes respectively); the 6845 is configured for a 2-pixel character height and the row address bit RA0 is used for bit 13 of the frame buffer address. This way, 200 vertical pixels can be used despite the 128 line limitation. Graphics mode on other systems used a similar trick: in the Hercules Graphics Card, bits 12-13 of the frame buffer address came from row address bits RA0-RA1, providing a vertical resolution of 348 pixels from 87 four-pixel-high "lines"; the Amstrad CPC used a line height of 8 just like in text mode, mapping row address RA0-RA2 to memory address MA11-MA13 and character address CA0-CA10 to memory address MA0-MA10. </p><p>These modes of operation were possible because the 6845 did not perform any buffering of character data. In the 1970s, 1980s, and to a lesser extent the 1990s, memory was expensive, fast memory was especially so, and this was an important concern. In the 1970s and early to mid-1980s, chip circuit densities were not very high either, and putting an 80-byte or larger character buffer into a chip like the 6845 might have enlarged the chip die by 50-100%, in turn making it more expensive by a few times that factor due to the exponential growth of chip defect rates and the consequent decline of production yield with die size. </p><p>On the other hand, the 6845 put the onus on its users to provide enough memory bandwidth to support rereading data on every line. If a character occupies one "word" in the video buffer, a display of <i>l</i> lines and <i>c</i> columns of characters with <i>s</i> scan lines per character requires <i>l</i> × <i>c</i> words of memory to represent a full screen of characters but takes <i>s</i> times that many memory accesses to complete one refresh cycle: each line of character words is repeatedly read <i>s</i> times before the next line is read. This means that character displays using the 6845 require high memory bandwidth on the order of the bandwidth required for all-points-addressable graphics displays of the same resolution. </p><p>A different video display controller that buffers one whole line of character data internally can avoid this repeated reading of each line of characters from the display buffer RAM, reducing the required memory bandwidth and allowing either slower, less expensive memory chips to be used, more time for a system CPU to access the memory, or a combination of both. Adding such a character buffer to the 6845 was deemed to not be cost-effective approach when the chip was introduced; however, only a few years later the <a href="/facts/MOS_VIC-II/3jLPsDD5">VIC-II</a> chip used on the Commodore 64 did include such a character line cache. </p> <h3>Limitations</h3> <p>Using the full address range RA0-RA4:CA0-CA13 the 6845 can address 214+5 = 524,288 words of memory. A word may be any number of bits chosen by the system designer as the memory width: though the number of unique addresses that the 6845 can address is limited to 524,288, the amount of memory that the 6845 can address may be significantly larger than might be assumed because the 6845 imposes no limit on the size of each memory location that it addresses. If the word size is one byte, as is often the case, the 6845 can address 512 <a href="/facts/Kibibyte/BNHUp9Qq">KiB</a>. If the word size is 32 bits, e.g. for 32-bit color graphics with one pixel per word, then the 6845 can address 2048 KiB; for 64-bit words, it can address twice as much. These limits arise from the combination of the 6845 and the design of the external memory connected to it, not from the 6845 alone. </p> <h3>Linear framebuffers</h3> <p>As described before, the 6845 cannot ordinarily provide large linear framebuffers. One design could only use 14-bit character addressing and set the number of lines per character to 1 but would be restricted to 128 lines and 16 KB of addressable memory. </p> <h2 id="differences-from-the-6545">Differences from the 6545</h2> <p>Although overwhelmingly compatible, a number of small variations exist between the 6845 and 6545. </p><p>The biggest difference is that the 6545 may be configured so that it has sole access to the address bus for video memory. Two additional registers are included for setting any address the CPU wishes to read and the chip alternates between outputting addresses for display generation and the display set for CPU access.<a class="footnote-ref" id="fnref:10" href="#fn:10"><sup>10</sup></a> </p><p>Smaller changes are that the <a href="/facts/MOS_Technology/1eKsjBS1">MOS Technology</a> and one variation of the <a href="/facts/Rockwell_International/dPSf6G1b">Rockwell</a> 6545 lack interlaced output support and all 6545s include an optional address skew, which delays display enable for one character cycle if set. This second feature was incorporated into later variations of the <a href="/facts/Motorola/ztqczx68">Motorola</a> 6845. The 6545 may be set to work in linear 14 bit mode using a status bit. On the 6845 the same thing requires adjustment of the character height.<a class="footnote-ref" id="fnref:11" href="#fn:11"><sup>11</sup></a> </p> <h2 id="tricks">Tricks</h2> <p>The 6845 reads the start address for its display once per <a href="/facts/Film_frame/27Uqo8WN">frame</a>. However, if the internal timing values on the chip are altered at the correct time it can be made to prepare for a new frame without ending the current one - creating a non-continuous break in generated addresses midway through the display. This is commonly used by <a href="/facts/Demoscene/yKunscS7">demos</a> and much more rarely <a href="/facts/Video_game/vmTdNASJ">games</a> to provide one moving area of the display (usually the play field) and one static (usually a status display). </p><p>Vertical scrolling appears constrained because only the character start address can be set and the row address is always zeroed at frame start, but by adjusting border times it is possible to shift the position the framebuffer is shown on the raster display for increments in between whole characters. With drawing of blank pixels at the screen edges, this can be made invisible to the user creating just the illusion of a smooth vertical scroll. </p> <h2 id="see-also">See also</h2> <ul><li><a href="/facts/Motorola_6847/4NlpBfRN">Motorola 6847</a>, a complete video display generator</li> <li><a href="/facts/List_of_home_computers_by_video_hardware/z3UBNAsS">List of home computers by video hardware</a></li></ul> <h2 id="external-links">External links</h2> Wikimedia Commons has media related to MC6845. <ul><li><a href="http://www.tinyvga.com/6845">HTML documentation of the 6845 registers</a></li> <li><a href="http://bbc.nvg.org/doc/datasheets/MC6845.zip">Zipped TIFs of the 6845 data sheets</a></li> <li><a href="http://www.6502.org/users/andre/hwinfo/crtc/diffs.html">Differences of CRTC models</a></li> <li><a href="http://archive.6502.org/appnotes/synertek_an3_6545_crtc.pdf">Synertek 6545 Application Note</a></li> <li><a href="https://mrboot.de/mc6845.php">MC6845 Timing Calculator, calculate register values</a></li> <li><a href="http://logon.system.free.fr/down/ACCC1.5-EN.pdf">Amstrad CPC CRTC 6845 Compendium</a></li></ul> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>"The 6845 Cathode Ray Tube Controller (CRTC)". www.tinyvga.com. Retrieved 2022-11-18. <a href="http://www.tinyvga.com/6845" target="_blank">http://www.tinyvga.com/6845</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>"Differences of CRTC models". www.6502.org. Retrieved 2022-11-18. <a href="http://www.6502.org/users/andre/hwinfo/crtc/diffs.html" target="_blank">http://www.6502.org/users/andre/hwinfo/crtc/diffs.html</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li> <li id="fn:3"><p>"The 6845 Cathode Ray Tube Controller (CRTC)". www.tinyvga.com. Retrieved 2022-11-18. <a href="http://www.tinyvga.com/6845" target="_blank">http://www.tinyvga.com/6845</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li> <li id="fn:4"><p>PC Mag Jul 1983, p. 435, at Google Books <a href="https://books.google.com/books?id=V2588uIxmAQC&pg=PA435" target="_blank">https://books.google.com/books?id=V2588uIxmAQC&pg=PA435</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li> <li id="fn:5"><p>"Datasheets-hitachi:hd4650" (PDF). Retrieved 2024-02-22. <a href="http://mess.redump.net/_media/datasheets/hitachi/hd46505.pdf" target="_blank">http://mess.redump.net/_media/datasheets/hitachi/hd46505.pdf</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></p></li> <li id="fn:6"><p>"Datasheet Archive: MB89321AP datasheet by Fujitsu". Datasheet Archive Search Engine. Retrieved 2024-02-22. <a href="https://www.datasheetarchive.com/datasheet?id=3561b572268fb0fe77cf81dc6909f0ff0f6bef&type=M&term=MB89321A" target="_blank">https://www.datasheetarchive.com/datasheet?id=3561b572268fb0fe77cf81dc6909f0ff0f6bef&type=M&term=MB89321A</a> <a href="#fnref:6" class="footnote-back-ref">↩</a></p></li> <li id="fn:7"><p>"The 6845 Cathode Ray Tube Controller (CRTC)". www.tinyvga.com. Retrieved 2022-11-18. <a href="http://www.tinyvga.com/6845" target="_blank">http://www.tinyvga.com/6845</a> <a href="#fnref:7" class="footnote-back-ref">↩</a></p></li> <li id="fn:8"><p>"The 6845 Cathode Ray Tube Controller (CRTC)". www.tinyvga.com. Retrieved 2022-11-18. <a href="http://www.tinyvga.com/6845" target="_blank">http://www.tinyvga.com/6845</a> <a href="#fnref:8" class="footnote-back-ref">↩</a></p></li> <li id="fn:9"><p>"The 6845 Cathode Ray Tube Controller (CRTC)". 2006-01-28. Retrieved 2024-02-22. <a href="http://andercheran.aiind.upv.es/~amstrad/docs/crtcnew.html" target="_blank">http://andercheran.aiind.upv.es/~amstrad/docs/crtcnew.html</a> <a href="#fnref:9" class="footnote-back-ref">↩</a></p></li> <li id="fn:10"><p>"Differences of CRTC models". www.6502.org. Retrieved 2022-11-18. <a href="http://www.6502.org/users/andre/hwinfo/crtc/diffs.html" target="_blank">http://www.6502.org/users/andre/hwinfo/crtc/diffs.html</a> <a href="#fnref:10" class="footnote-back-ref">↩</a></p></li> <li id="fn:11"><p>Fachat, André (2013-11-02). "Differences of CRTC models". 6502.org. Retrieved 2024-02-22. <a href="http://www.6502.org/users/andre/hwinfo/crtc/diffs.html" target="_blank">http://www.6502.org/users/andre/hwinfo/crtc/diffs.html</a> <a href="#fnref:11" class="footnote-back-ref">↩</a></p></li> </ol>