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<h2 id="2-level-logic">2-level logic</h2> <p>In binary logic the two levels are logical high and logical low, which generally correspond to <a href="/facts/Binary_number/a6JDSRPs">binary numbers</a> 1 and 0 respectively or <a href="/facts/Truth_value/SY4e2w8l">truth values</a> <i>true</i> and <i>false</i> respectively. Signals with one of these two levels can be used in <a href="/facts/Boolean_algebra/VkCToAmg">Boolean algebra</a> for digital circuit design or analysis. </p> <h3>Active state</h3> <p>The use of either the higher or the lower voltage level to represent either logic state is arbitrary. The two options are active high (<i>positive logic</i>) and active low (<i>negative logic</i>). Active-high and active-low states can be mixed at will: for example, a <a href="/facts/Read_only_memory/P9QMuDLH">read only memory</a> integrated circuit may have a chip-select signal that is active-low, but the data and address bits are conventionally active-high. Occasionally a logic design is simplified by inverting the choice of active level (see <a href="/facts/De_Morgan%2527s_laws/dj3F8xpt">De Morgan's laws</a>). </p> Binary signal representations<table><tbody><tr><th>Logic level</th><th>Active-high signal</th><th>Active-low signal</th></tr><tr><td>Logical high</td><td>1</td><td>0</td></tr><tr><td>Logical low</td><td>0</td><td>1</td></tr></tbody></table> <p>The name of an active-low signal is historically written with a bar above it to distinguish it from an active-high signal. For example, the name Q, read <i>Q bar</i> or <i>Q not</i>, represents an active-low signal. The conventions commonly used are: </p> <ul><li>a bar above (Q)</li> <li>a leading slash (/Q)</li> <li>a leading exclamation mark (!Q)</li> <li>a lower-case <i>n</i> prefix or suffix (nQ, Qn or Q_n)</li> <li>an upper-case <i>N</i> suffix (Q_N)</li> <li>a trailing <a href="/facts/Number_sign/bHYCsWs1">#</a> (Q#), or</li> <li>an _B or _L suffix (Q_B or Q_L).<a class="footnote-ref" id="fnref:1" href="#fn:1"><sup>1</sup></a></li></ul> <p>Many control signals in electronics are active-low signals<a class="footnote-ref" id="fnref:2" href="#fn:2"><sup>2</sup></a> (usually reset lines, chip-select lines and so on). Logic families such as <a href="/facts/Transistor-transistor_logic/z4bvHotl">TTL</a> can sink more current than they can source, so <a href="/facts/Fanout/lCm5joyw">fanout</a> and <a href="/facts/Noise_immunity/nflP7hMM">noise immunity</a> increase. It also allows for <a href="/facts/Wired-OR/1YduGEtl">wired-OR</a> logic if the logic gates are <a href="/facts/Open-collector/E12DL8fL">open-collector</a>/<a href="/facts/Open-drain/E12DL8fL">open-drain</a> with a pull-up resistor. Examples of this are the <a href="/facts/I%25C2%25B2C/dKBBhs4U">I²C</a> bus, <a href="/facts/Controller_Area_Network/EGxoS88W">CAN</a> bus, and <a href="/facts/Peripheral_Component_Interconnect/n6CGuFvP">PCI</a> bus. </p><p>Some signals have a meaning in both states and notation may indicate such. For example, it is common to have a read/write line designated R/W, indicating that the signal is high in case of a read and low in case of a write. </p> <h3>Logic voltage levels</h3> <p>The two logical states are usually represented by two different voltages, but two different <a href="/facts/Electric_current/Dc1xdnUX">currents</a> are used in some logic signaling, like <a href="/facts/Digital_current_loop_interface/Xdl2y03S">digital current loop interface</a> and <a href="/facts/Current-mode_logic/nBzkH5vL">current-mode logic</a>. High and low thresholds are specified for each logic family. When below the low threshold, the signal is <i>low</i>. When above the high threshold, the signal is <i>high</i>. Intermediate levels are undefined, resulting in highly implementation-specific circuit behavior. </p><p>It is usual to allow some tolerance in the voltage levels used; for example, 0 to 2 volts might represent logic 0, and 3 to 5 volts logic 1. A voltage of 2 to 3 volts would be invalid and occur only in a fault condition or during a logic-level transition. However, few logic circuits can detect such a condition, and most devices will interpret the signal simply as high or low in an undefined or device-specific manner. Some logic devices incorporate <a href="/facts/Schmitt_trigger/TzjbP3dD">Schmitt trigger</a> inputs, whose behavior is much better defined in the threshold region and have increased resilience to small variations in the input voltage. The problem of the circuit designer is to avoid circumstances that produce intermediate levels, so that the circuit behaves predictably. </p> Examples of binary logic levels<table><tbody><tr><th>Technology</th><th>L voltage</th><th>H voltage</th><th>Notes</th></tr><tr><td><a href="/facts/CMOS/7g2EwHGA">CMOS</a><a class="footnote-ref" id="fnref:3" href="#fn:3"><sup>3</sup></a><a class="footnote-ref" id="fnref:4" href="#fn:4"><sup>4</sup></a></td><td>0 V to 30% VDD</td><td>70% VDD to VDD</td><td>VDD = <a href="/facts/IC_power_supply_pin/moPAAjnl">supply voltage</a></td></tr><tr><td><a href="/facts/Transistor-transistor_logic/z4bvHotl">TTL</a><a class="footnote-ref" id="fnref:5" href="#fn:5"><sup>5</sup></a></td><td>0 V to 0.8 V</td><td>2 V to VCC</td><td>VCC = 5 V ±5% (7400 commercial family) or ±10% (5400 military family)</td></tr></tbody></table> <p>Nearly all digital circuits use a consistent logic level for all internal signals. That level, however, varies from one system to another. Interconnecting any two logic families often required special techniques such as additional <a href="/facts/Pull-up_resistor/zeEjjrqk">pull-up resistors</a> or purpose-built interface circuits known as level shifters. A <a href="/facts/Level_shifter/4Xn5qo2K">level shifter</a> connects one digital circuit that uses one logic level to another digital circuit that uses another logic level. Often two level shifters are used, one at each system: A <a href="/facts/Line_driver/axaAuf8z">line driver</a> converts from internal logic levels to standard interface line levels; a line receiver converts from interface levels to internal voltage levels. </p><p>For example, <a href="/facts/Transistor%25E2%2580%2593transistor_logic/z4bvHotl">TTL</a> levels are different from those of <a href="/facts/CMOS/7g2EwHGA">CMOS</a>. Generally, a TTL output does not rise high enough to be reliably recognized as a logic 1 by a CMOS input, especially if it is only connected to a high-input-impedance CMOS input that does not source significant current. This problem was solved by the invention of the 74HCT family of devices that uses CMOS technology but TTL input logic levels. These devices only work with a 5 V power supply. </p> Logic supply voltages<table><tbody><tr><th>Supply voltage</th><th>Technology</th><th>Logic families (examples)</th><th>Reference</th></tr><tr><td>5V, 10V, 15V</td><td>Metal <a href="/facts/CMOS/7g2EwHGA">CMOS</a></td><td><a href="/facts/4000-series_integrated_circuits/x505SAg7">4000</a>, <a href="/facts/7400-series_integrated_circuits/mDqHhWyc">74C</a></td><td><a class="footnote-ref" id="fnref:6" href="#fn:6"><sup>6</sup></a></td></tr><tr><td>5V</td><td><a href="/facts/Transistor%25E2%2580%2593transistor_logic/z4bvHotl">TTL</a></td><td><a href="/facts/7400-series_integrated_circuits/mDqHhWyc">7400</a>, 74S, 74LS, 74ALS, 74F, 74H</td><td><a class="footnote-ref" id="fnref:7" href="#fn:7"><sup>7</sup></a></td></tr><tr><td>5V</td><td><a href="/facts/BiCMOS/RF6LspQ0">BiCMOS</a></td><td>74ABT, 74BCT</td><td></td></tr><tr><td>5V</td><td><a href="/facts/CMOS/7g2EwHGA">CMOS</a> (TTL I/O)</td><td><a href="/facts/7400-series_integrated_circuits/mDqHhWyc">74HCT</a>, 74AHCT, 74ACT</td><td><a class="footnote-ref" id="fnref:8" href="#fn:8"><sup>8</sup></a></td></tr><tr><td>3.3V, 5V</td><td><a href="/facts/CMOS/7g2EwHGA">CMOS</a></td><td><a href="/facts/7400-series_integrated_circuits/mDqHhWyc">74HC</a>, 74AHC, 74AC</td><td><a class="footnote-ref" id="fnref:9" href="#fn:9"><sup>9</sup></a><a class="footnote-ref" id="fnref:10" href="#fn:10"><sup>10</sup></a></td></tr><tr><td>5V</td><td><a href="/facts/LVCMOS/5cDjEpda">LVCMOS</a></td><td><a href="/facts/7400-series_integrated_circuits/mDqHhWyc">74LVC</a>, 74AXP</td><td><a class="footnote-ref" id="fnref:11" href="#fn:11"><sup>11</sup></a></td></tr><tr><td>3.3V</td><td>LVCMOS</td><td>74LVC, 74AUP, 74AXC, 74AXP</td><td><a class="footnote-ref" id="fnref:12" href="#fn:12"><sup>12</sup></a></td></tr><tr><td>2.5V</td><td>LVCMOS</td><td>74LVC, 74AUP, 74AUC, 74AXC, 74AXP</td><td><a class="footnote-ref" id="fnref:13" href="#fn:13"><sup>13</sup></a></td></tr><tr><td>1.8V</td><td>LVCMOS</td><td>74LVC, 74AUP, 74AUC, 74AXC, 74AXP</td><td><a class="footnote-ref" id="fnref:14" href="#fn:14"><sup>14</sup></a></td></tr><tr><td>1.5V</td><td>LVCMOS</td><td>74AUP, 74AUC, 74AXC, 74AXP</td><td><a class="footnote-ref" id="fnref:15" href="#fn:15"><sup>15</sup></a></td></tr><tr><td>1.2V</td><td>LVCMOS</td><td>74AUP, 74AUC, 74AXC, 74AXP</td><td><a class="footnote-ref" id="fnref:16" href="#fn:16"><sup>16</sup></a></td></tr></tbody></table> <h2 id="more-than-two-levels">More than two levels</h2> <h3>3-value logic</h3> <p>Though rare, <a href="/facts/Ternary_computer/tU1DI6wo">ternary computers</a> evaluate <a href="/facts/Base_3/bMUfR74P">base 3</a> <a href="/facts/Three-valued_logic/k4vMkwRL">three-valued or ternary logic</a> using 3 voltage levels. </p> <h3>3-state logic</h3> <p>In <a href="/facts/Three-state_logic/SD6wXHNN">three-state logic</a>, an output device can be in one of three possible states: 0, 1, or Z, with the last meaning <a href="/facts/High_impedance/DNNoHHvQ">high impedance</a>. This is not a voltage or logic level, but means that the output is not controlling the state of the connected circuit. </p> <h3>4-value logic</h3> <p><a href="/facts/Four_valued_logic/faGUrw8E">Four valued logic</a> adds a fourth state, X (<i>don't care</i>), meaning the value of the signal is unimportant and undefined. It means that an input is undefined, or an output signal may be chosen for implementation convenience (see <a href="/facts/Karnaugh_map/saFd8oNl">Karnaugh map § Don't cares</a>). </p> <h3>9-level logic</h3> <p><a href="/facts/IEEE_1164/IVj9jTjf">IEEE 1164</a> defines 9 logic states for use in <a href="/facts/Electronic_design_automation/o4la3fmX">electronic design automation</a>. The standard includes strong and weakly driven signals, high impedance and unknown and uninitialized states. </p> <h3>Multi-level cells</h3> <p>In solid-state storage devices, a <a href="/facts/Multi-level_cell/nBqK3614">multi-level cell</a> stores data using multiple voltages. Storing n bits in one cell requires the device to reliably distinguish 2n distinct voltage levels. </p> <h3>Line coding</h3> <p>Digital <a href="/facts/Line_code/x9IuaYNL">line codes</a> may use more than two states to encode and transmit data more efficiently. Examples include <a href="/facts/Alternate_mark_inversion/I84wDjmR">alternate mark inversion</a> and <a href="/facts/4B3T/1XvwK38X">4B3T</a> from telecommunications, and <a href="/facts/Pulse-amplitude_modulation/Y30VmMJI">pulse-amplitude modulation</a> variants used by <a href="/facts/Ethernet_over_twisted_pair/2jRlgJb4">Ethernet over twisted pair</a>. For instance, <a href="/facts/100BASE-TX/YM5HjX0C">100BASE-TX</a> uses <a href="/facts/MLT-3_encoding/7qGmBQBx">MLT-3 encoding</a> with three <a href="/facts/Differential_signalling/jusjFQKo">differential</a> voltage levels (−1V, 0V, +1V) while <a href="/facts/1000BASE-T/1ItIoV2w">1000BASE-T</a> encodes data using five differential voltage levels (−1V, −0.5V, 0V, +0.5V, +1V).<a class="footnote-ref" id="fnref:17" href="#fn:17"><sup>17</sup></a> Once received, the line coding is converted back to binary. </p> <h2 id="see-also">See also</h2> <ul><li><a href="/facts/Logic_family/QlEgIecX">Logic family</a></li> <li><a href="/facts/Digital_current_loop_interface/Xdl2y03S">Digital current loop interface</a></li></ul> <h2 id="external-links">External links</h2> <ul><li><a href="http://www.cs.ualberta.ca/~amaral/courses/329/webslides/Topic2-DeMorganLaws/sld017.htm">Positive Logic (active-high) and Negative logic (active-low )</a></li> <li><a href="http://delphys.net/d.holmes/hardware/levelshift.html">Simple MOSFET-based logic level conversion or level-shift based on work done by Herman Schutte at Philips Semiconductors Systems Laboratory in Eindhoven</a></li></ul> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>"Coding Style Guidelines" (PDF). Xilinx. Retrieved 2017-08-17. <a href="https://wiki.electroniciens.cnrs.fr/images/Xilinx_HDL_Coding_style.pdf" target="_blank">https://wiki.electroniciens.cnrs.fr/images/Xilinx_HDL_Coding_style.pdf</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>Balch, Mark (2003). Complete Digital Design: A Comprehensive Guide To Digital Electronics And Computer System Architecture. McGraw-Hill Professional. p. 430. ISBN 978-0-07-140927-8. <a href="978-0-07-140927-8" target="_blank">978-0-07-140927-8</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li> <li id="fn:3"><p>"Logic signal voltage levels". All About Circuits. Retrieved 2015-03-29. <a href="http://www.allaboutcircuits.com/vol_4/chpt_3/10.html" target="_blank">http://www.allaboutcircuits.com/vol_4/chpt_3/10.html</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li> <li id="fn:4"><p>"HEF4000B Family Specifications" (PDF). Philips Semiconductors. January 1995. Archived from the original (PDF) on March 4, 2016. Parametric limits are guaranteed for VDD of 5V, 10V, and 15V. <a href="https://web.archive.org/web/20160304052639/http://www.nxp.com/documents/data_sheet_addendum/familyhef4000specification.pdf" target="_blank">https://web.archive.org/web/20160304052639/http://www.nxp.com/documents/data_sheet_addendum/familyhef4000specification.pdf</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li> <li id="fn:5"><p>"Logic signal voltage levels". All About Circuits. Retrieved 2015-03-29. <a href="http://www.allaboutcircuits.com/vol_4/chpt_3/10.html" target="_blank">http://www.allaboutcircuits.com/vol_4/chpt_3/10.html</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></p></li> <li id="fn:6"><p>"HEF4000B Family Specifications" (PDF). Philips Semiconductors. January 1995. Archived from the original (PDF) on March 4, 2016. Parametric limits are guaranteed for VDD of 5V, 10V, and 15V. <a href="https://web.archive.org/web/20160304052639/http://www.nxp.com/documents/data_sheet_addendum/familyhef4000specification.pdf" target="_blank">https://web.archive.org/web/20160304052639/http://www.nxp.com/documents/data_sheet_addendum/familyhef4000specification.pdf</a> <a href="#fnref:6" class="footnote-back-ref">↩</a></p></li> <li id="fn:7"><p>"AppNote 319 - Comparison of MM74HC to 74LS, 74S and 74ALS Logic" (PDF). Fairchild Semiconductor. June 1983. Archived (PDF) from the original on October 24, 2021. <a href="https://www.onsemi.com/pub/Collateral/AN-319.pdf" target="_blank">https://www.onsemi.com/pub/Collateral/AN-319.pdf</a> <a href="#fnref:7" class="footnote-back-ref">↩</a></p></li> <li id="fn:8"><p>"AHC/AHCT Designer's Guide" (PDF). Texas Instruments. September 1998. Archived (PDF) from the original on April 13, 2018. Technical Comparison of AHC / HC / AC (CMOS I/O) and AHCT / HCT / ACT (TTL I/O) Logic Families <a href="https://www.ti.com/lit/ml/scla013d/scla013d.pdf" target="_blank">https://www.ti.com/lit/ml/scla013d/scla013d.pdf</a> <a href="#fnref:8" class="footnote-back-ref">↩</a></p></li> <li id="fn:9"><p>"AppNote 319 - Comparison of MM74HC to 74LS, 74S and 74ALS Logic" (PDF). Fairchild Semiconductor. June 1983. Archived (PDF) from the original on October 24, 2021. <a href="https://www.onsemi.com/pub/Collateral/AN-319.pdf" target="_blank">https://www.onsemi.com/pub/Collateral/AN-319.pdf</a> <a href="#fnref:9" class="footnote-back-ref">↩</a></p></li> <li id="fn:10"><p>"AHC/AHCT Designer's Guide" (PDF). Texas Instruments. September 1998. Archived (PDF) from the original on April 13, 2018. Technical Comparison of AHC / HC / AC (CMOS I/O) and AHCT / HCT / ACT (TTL I/O) Logic Families <a href="https://www.ti.com/lit/ml/scla013d/scla013d.pdf" target="_blank">https://www.ti.com/lit/ml/scla013d/scla013d.pdf</a> <a href="#fnref:10" class="footnote-back-ref">↩</a></p></li> <li id="fn:11"><p>"Little Logic Guide" (PDF). Texas Instruments. 2018. Archived (PDF) from the original on April 3, 2021. Logic Voltage Graph (page4) <a href="https://www.ti.com/lit/sg/scyt129g/scyt129g.pdf" target="_blank">https://www.ti.com/lit/sg/scyt129g/scyt129g.pdf</a> <a href="#fnref:11" class="footnote-back-ref">↩</a></p></li> <li id="fn:12"><p>"Little Logic Guide" (PDF). Texas Instruments. 2018. Archived (PDF) from the original on April 3, 2021. Logic Voltage Graph (page4) <a href="https://www.ti.com/lit/sg/scyt129g/scyt129g.pdf" target="_blank">https://www.ti.com/lit/sg/scyt129g/scyt129g.pdf</a> <a href="#fnref:12" class="footnote-back-ref">↩</a></p></li> <li id="fn:13"><p>"Little Logic Guide" (PDF). Texas Instruments. 2018. Archived (PDF) from the original on April 3, 2021. Logic Voltage Graph (page4) <a href="https://www.ti.com/lit/sg/scyt129g/scyt129g.pdf" target="_blank">https://www.ti.com/lit/sg/scyt129g/scyt129g.pdf</a> <a href="#fnref:13" class="footnote-back-ref">↩</a></p></li> <li id="fn:14"><p>"Little Logic Guide" (PDF). Texas Instruments. 2018. Archived (PDF) from the original on April 3, 2021. Logic Voltage Graph (page4) <a href="https://www.ti.com/lit/sg/scyt129g/scyt129g.pdf" target="_blank">https://www.ti.com/lit/sg/scyt129g/scyt129g.pdf</a> <a href="#fnref:14" class="footnote-back-ref">↩</a></p></li> <li id="fn:15"><p>"Little Logic Guide" (PDF). Texas Instruments. 2018. Archived (PDF) from the original on April 3, 2021. Logic Voltage Graph (page4) <a href="https://www.ti.com/lit/sg/scyt129g/scyt129g.pdf" target="_blank">https://www.ti.com/lit/sg/scyt129g/scyt129g.pdf</a> <a href="#fnref:15" class="footnote-back-ref">↩</a></p></li> <li id="fn:16"><p>"Little Logic Guide" (PDF). Texas Instruments. 2018. Archived (PDF) from the original on April 3, 2021. Logic Voltage Graph (page4) <a href="https://www.ti.com/lit/sg/scyt129g/scyt129g.pdf" target="_blank">https://www.ti.com/lit/sg/scyt129g/scyt129g.pdf</a> <a href="#fnref:16" class="footnote-back-ref">↩</a></p></li> <li id="fn:17"><p>Thompson, Geoff (13 November 1997). How 1000BASE-T Works (PDF). IEEE802.3 Plenary. Montreal. Retrieved 2023-11-21. <a href="https://grouper.ieee.org/groups/802/3/ab/public/nov97/geoff1.pdf#page=3" target="_blank">https://grouper.ieee.org/groups/802/3/ab/public/nov97/geoff1.pdf#page=3</a> <a href="#fnref:17" class="footnote-back-ref">↩</a></p></li> </ol>