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Programmable ROM
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<h2 id="history">History</h2> <p>The PROM was invented in 1956 by <a href="/facts/Wen_Tsing_Chow/gcD2nL8F">Wen Tsing Chow</a>, working for the Arma Division of the American <a href="/facts/Bosch_(company)/wPuk1Udv">Bosch</a> Arma Corporation in <a href="/facts/Garden_City%2c_New_York/V1ykBhVk">Garden City</a>, <a href="/facts/New_York_(state)/mnl67G1G">New York</a>.<a class="footnote-ref" id="fnref:2" href="#fn:2"><sup>2</sup></a><a class="footnote-ref" id="fnref:3" href="#fn:3"><sup>3</sup></a> The invention was conceived at the request of the <a href="/facts/United_States_Air_Force/7MxWBYlc">United States Air Force</a> to come up with a more flexible and secure way of storing the targeting constants in the Atlas E/F <a href="/facts/ICBM/0vKnj2Y7">ICBM</a>'s airborne digital computer. The patent and associated technology were held under secrecy order for several years while the Atlas E/F was the main operational missile of the United States ICBM force. The term <i>burn</i>, referring to the process of programming a PROM, is also in the original patent, as one of the original implementations was to literally burn the internal whiskers of diodes with a current overload to produce a circuit discontinuity. The first PROM programming machines were also developed by Arma engineers under Chow's direction and were located in Arma's Garden City lab and Air Force <a href="/facts/Strategic_Air_Command/Qp0Y5xpB">Strategic Air Command</a> (SAC) headquarters. </p> <h3>One time programmable memory</h3> <p>OTP (one time programmable) memory is a special type of <a href="/facts/Non-volatile_memory/EN72wMD9">non-volatile memory</a> (NVM) that permits data to be written to memory only once. Once the memory has been programmed, it retains its value upon loss of power (i.e., is non-volatile). OTP memory is used in applications where reliable and repeatable reading of data is required. Examples include boot code, encryption keys and configuration parameters for analog, sensor or display circuitry. OTP NVM is characterized, over other types of NVM like <a href="/facts/EFuse/RGCBay7S">eFuse</a> or EEPROM, by offering a low power, small area footprint memory structure. As such OTP memory finds application in products from microprocessors & display drivers to Power Management ICs (PMICs). </p><p>Commercially available semiconductor antifuse-based OTP memory arrays have been around at least since 1969, with initial antifuse bit cells dependent on blowing a capacitor between crossing conductive lines. <a href="/facts/Texas_Instruments/88NUhuHF">Texas Instruments</a> developed a MOS <a href="/facts/Gate_oxide/84kcAbyL">gate oxide</a> breakdown antifuse in 1979.<a class="footnote-ref" id="fnref:4" href="#fn:4"><sup>4</sup></a> A dual-gate-oxide two-transistor (2T) MOS antifuse was introduced in 1982.<a class="footnote-ref" id="fnref:5" href="#fn:5"><sup>5</sup></a> Early oxide breakdown technologies exhibited a variety of scaling, programming, size and manufacturing problems that prevented volume production of memory devices based on these technologies. </p><p>Another form of one-time programmable memory device uses the same semiconductor chip as an ultraviolet-<a href="/facts/EPROM/kXcEca36">erasable programmable read-only memory</a> (UV-EPROM), but the finished device is put into an opaque package, instead of the expensive ceramic package with transparent quartz window required for erasing. These devices are programmed with the same methods as the UV EPROM parts but are less costly. Embedded controllers may be available in both field-erasable and one-time styles, allowing a cost saving in volume production without the expense and lead time of factory-programmed mask ROM chips. <a class="footnote-ref" id="fnref:6" href="#fn:6"><sup>6</sup></a> </p><p>Although antifuse-based PROM has been available for decades, it wasn’t available in standard <a href="/facts/CMOS/7g2EwHGA">CMOS</a> until 2001 when Kilopass Technology Inc. patented 1T, 2T, and 3.5T antifuse bit cell technologies using a standard CMOS process, enabling integration of PROM into logic CMOS chips. The first process node antifuse can be implemented in standard CMOS is 0.18 um. Since the gate oxide breakdown is less than the junction breakdown, special diffusion steps were not required to create the antifuse programming element. In 2005, a split channel antifuse device<a class="footnote-ref" id="fnref:7" href="#fn:7"><sup>7</sup></a> was introduced by Sidense. This split channel bit cell combines the thick (IO) and thin (gate) oxide devices into one transistor (1T) with a common <a href="/facts/Polycrystalline_silicon/NdywIRGW">polysilicon</a> gate. </p> <h2 id="programming">Programming</h2> <p>A typical PROM comes with all bits reading as "1". Burning a fuse bit during programming causes the bit to be read as "0" by "blowing" the fuses, which is an irreversible process. Some devices can be "reprogrammed" if the new data replaces "1"s with "0"s. Some CPU instruction sets (e.g. <a href="/facts/MOS_Technology_6502/q9YLwkzm">6502</a>) took advantage of this by defining a break (BRK) instruction with the operation code of '00'. In cases where there was an incorrect instruction, it could be "reprogrammed" to a BRK causing the CPU to transfer control to a patch. This would execute the correct instruction and return to the instruction after the BRK. </p><p>The bit cell is programmed by applying a high-voltage pulse not encountered during a normal operation across the gate and substrate of the thin oxide transistor (around 6 V for a 2 nm thick oxide, or 30 MV/cm) to break down the oxide between gate and substrate. The positive voltage on the transistor's gate forms an inversion channel in the substrate below the gate, causing a tunneling current to flow through the oxide. The current produces additional traps in the oxide, increasing the current through the oxide and ultimately melting the oxide and forming a conductive channel from gate to substrate. The current required to form the conductive channel is around 100 μA/100 nm2 and the breakdown occurs in approximately 100 μs or less.<a class="footnote-ref" id="fnref:8" href="#fn:8"><sup>8</sup></a> </p> <h2 id="see-also">See also</h2> <ul><li><a href="/facts/Intel_HEX/2LWl2u83">Intel HEX</a></li></ul> <h2 id="references">References</h2> <ul><li><a href="https://archive.org/details/bitsavers_inteldataBMay77_21293903">1977 Intel Memory Design Handbook</a> - archive.org</li> <li><a href="https://web.archive.org/web/20130812120201/http://www.intel-vintage.info/intelmemory.htm">Intel PROM datasheets</a>[<i>usurped</i>] - intel-vintage.info</li> <li>View the US "Switch Matrix" Patent #3028659 at <a href="http://patimg2.uspto.gov/.piw?Docid=03028659&idkey=NONE">US Patent Office</a> <a href="https://web.archive.org/web/20151016080757/http://patimg2.uspto.gov/.piw?Docid=03028659&idkey=NONE">Archived</a> 2015-10-16 at the <a href="/facts/Wayback_Machine/nmQ3a6JC">Wayback Machine</a> or <a href="https://patents.google.com/patent/US3028659">Google</a></li> <li>View Kilopass Technology Patent US "High density semiconductor memory cell and memory array using a single transistor and having variable gate oxide breakdown" Patent #6940751 at <a href="http://patimg2.uspto.gov/.piw?Docid=6940751&idkey=NONE">US Patent Office</a> <a href="https://web.archive.org/web/20150904051044/http://patimg2.uspto.gov/.piw?Docid=6940751&idkey=NONE">Archived</a> 2015-09-04 at the <a href="/facts/Wayback_Machine/nmQ3a6JC">Wayback Machine</a> or <a href="https://patents.google.com/patent/US6940751">Google</a></li> <li>View Sidense US "Split Channel Antifuse Array Architecture" Patent #7402855 at <a href="http://patimg2.uspto.gov/.piw?Docid=7402855&idkey=NONE">US Patent Office</a> <a href="https://web.archive.org/web/20150904051044/http://patimg2.uspto.gov/.piw?Docid=7402855&idkey=NONE">Archived</a> 2015-09-04 at the <a href="/facts/Wayback_Machine/nmQ3a6JC">Wayback Machine</a> or <a href="https://patents.google.com/patent/US20060244099">Google</a></li> <li>View the US "Method of Manufacturing Semiconductor Integrated Circuits" Patent #3634929 at <a href="http://patimg2.uspto.gov/.piw?Docid=3634929&idkey=NONE">US Patent Office</a> <a href="https://web.archive.org/web/20150904051044/http://patimg2.uspto.gov/.piw?Docid=3634929&idkey=NONE">Archived</a> 2015-09-04 at the <a href="/facts/Wayback_Machine/nmQ3a6JC">Wayback Machine</a> or <a href="https://patents.google.com/patent/US3634929">Google</a></li> <li>CHOI et al. (2008). <a href="https://wayback.archive-it.org/all/20081031153339/http://www.ee.ucla.edu/~ipl/New_Non-Volatile_Memory_Structures_for_FPGA_Architectures.pdf">"New Non-Volatile Memory Structures for FPGA Architectures"</a>[<i>usurped</i>]</li> <li>For the Advantages and Disadvantages table, see Ramamoorthy, G: "Dataquest Insight: Nonvolatile Memory IP Market, Worldwide, 2008-2013", page 10. Gartner, 2009</li></ul> <h2 id="see-also">See also</h2> <ul><li><a href="/facts/EPROM/kXcEca36">EPROM</a></li> <li><a href="/facts/EEPROM/0yAMFY0I">EEPROM</a></li></ul> <h2 id="external-links">External links</h2> <ul><li><a href="http://www.righto.com/2019/07/looking-inside-1970s-prom-chip-that.html">Looking inside a 1970s PROM chip that stores data in microscopic fuse</a> - shows die of a 256x4 MMI 5300 PROM</li></ul> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>Whitaker, Jerry C. (3 October 2018). The Electronics Handbook. CRC Press. ISBN 978-1-4200-3666-4. <a href="978-1-4200-3666-4" target="_blank">978-1-4200-3666-4</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>Han-Way Huang (5 December 2008). Embedded System Design with C805. Cengage Learning. p. 22. ISBN 978-1-111-81079-5. Archived from the original on 27 April 2018. <a href="978-1-111-81079-5" target="_blank">978-1-111-81079-5</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li> <li id="fn:3"><p>Marie-Aude Aufaure; Esteban Zimányi (17 January 2013). Business Intelligence: Second European Summer School, eBISS 2012, Brussels, Belgium, July 15-21, 2012, Tutorial Lectures. Springer. p. 136. ISBN 978-3-642-36318-4. Archived from the original on 27 April 2018. <a href="978-3-642-36318-4" target="_blank">978-3-642-36318-4</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li> <li id="fn:4"><p>See US Patent 4184207 Archived 2018-04-27 at the Wayback Machine - High density floating gate electrically programmable ROM, and US Patent 4151021 Archived 2018-04-27 at the Wayback Machine - Method of making a high density floating gate electrically programmable ROM <a href="http://patimg2.uspto.gov/.piw?Docid=4184207&idkey=NONE" target="_blank">http://patimg2.uspto.gov/.piw?Docid=4184207&idkey=NONE</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li> <li id="fn:5"><p>Chip Planning Portal. ChipEstimate.com. Retrieved on 2013-08-10. <a href="http://www.chipestimate.com/techtalk/techtalk_071218.html" target="_blank">http://www.chipestimate.com/techtalk/techtalk_071218.html</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></p></li> <li id="fn:6"><p>Ken Arnold, "Embedded Controller Hardware Design", Newnes, 2004, ISBN 1-878707-52-3, page 102 <a href="#fnref:6" class="footnote-back-ref">↩</a></p></li> <li id="fn:7"><p>See US Patent 7402855 Archived 2015-09-04 at the Wayback Machine split channel antifuse device <a href="http://patimg2.uspto.gov/.piw?Docid=7402855&idkey=NONE" target="_blank">http://patimg2.uspto.gov/.piw?Docid=7402855&idkey=NONE</a> <a href="#fnref:7" class="footnote-back-ref">↩</a></p></li> <li id="fn:8"><p>Wlodek Kurjanowicz (2008). "Evaluating Embedded Non-Volatile Memory for 65nm and Beyond" (PDF). Archived from the original (PDF) on 2016-03-04. Retrieved 2009-09-04. <a href="https://web.archive.org/web/20160304025935/http://www.sidense.com/images/stories/designcon_8_a_eval_embedded_nvm_65nm_and_beyond.pdf" target="_blank">https://web.archive.org/web/20160304025935/http://www.sidense.com/images/stories/designcon_8_a_eval_embedded_nvm_65nm_and_beyond.pdf</a> <a href="#fnref:8" class="footnote-back-ref">↩</a></p></li> </ol>