Cycles per instruction

<h2 id="definition">Definition</h2>
<p>The average of Cycles Per Instruction in a given process (CPI) is defined by the following <a href="/facts/Weighted_arithmetic_mean/VHyJfPxb">weighted average</a>:
</p>

C
          P
          I
        
        :=
        
          
            
              
                Σ
                
                  i
                
              
              (
              
                
                  I
                  C
                
                
                  i
                
              
              )
              (
              
                
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                  C
                
                
                  i
                
              
              )
            
            
              I
              C
            
          
        
        =
        
          
            
              
                Σ
                
                  i
                
              
              (
              
                
                  I
                  C
                
                
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              ⋅
              
                
                  C
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              )
            
            
              
                Σ
                
                  i
                
              
              (
              
                
                  I
                  C
                
                
                  i
                
              
              )
            
          
        
      
    
    {\displaystyle \mathrm {CPI} :={\frac {\Sigma _{i}(\mathrm {IC} _{i})(\mathrm {CC} _{i})}{\mathrm {IC} }}={\frac {\Sigma _{i}(\mathrm {IC} _{i}\cdot \mathrm {CC} _{i})}{\Sigma _{i}(\mathrm {IC} _{i})}}}

<p>Where 
  
    
      
        
          
            I
            C
          
          
            i
          
        
      
    
    {\displaystyle \mathrm {IC} _{i}}
  
 is the number of instructions for a given instruction type 
  
    
      
        i
      
    
    {\displaystyle i}
  
, 
  
    
      
        
          
            C
            C
          
          
            i
          
        
      
    
    {\displaystyle \mathrm {CC} _{i}}
  
 is the clock-cycles for that instruction type and 
  
    
      
        
          I
          C
        
        =
        
          Σ
          
            i
          
        
        (
        
          
            I
            C
          
          
            i
          
        
        )
      
    
    {\displaystyle \mathrm {IC} =\Sigma _{i}(\mathrm {IC} _{i})}
  
 is the total instruction count. The summation sums over all instruction types for a given benchmarking process.
</p>
<h2 id="explanation">Explanation</h2>
<p>Let us assume a <a href="/facts/Classic_RISC_pipeline/67UhbP04">classic RISC pipeline</a>, with the following five stages:
</p>
<ol><li>Instruction fetch cycle (IF).</li>
<li>Instruction decode/Register fetch cycle (ID).</li>
<li>Execution/Effective address cycle (EX).</li>
<li>Memory access (MEM).</li>
<li>Write-back cycle (WB).</li></ol>
<p>Each stage requires one clock cycle and an instruction passes through the stages sequentially. Without <a href="/facts/Instruction_pipelining/3zy6CcX1">pipelining</a>, in a <a href="/facts/Multi-cycle_processor/MyzCbpDP">multi-cycle processor</a>, a new instruction is fetched in stage 1 only after the previous instruction finishes at stage 5, therefore the number of clock cycles it takes to execute an instruction is five (CPI = 5 > 1). In this case, the processor is said to be <i>subscalar</i>. With pipelining, a new instruction is fetched every clock cycle by exploiting <a href="/facts/Instruction-level_parallelism/2W8qvN8K">instruction-level parallelism</a>, therefore, since one could theoretically have five instructions in the five pipeline stages at once (one instruction per stage), a different instruction would complete stage 5 in every clock cycle and on average the number of clock cycles it takes to execute an instruction is 1 (CPI = 1). In this case, the processor is said to be <i>scalar</i>.
</p><p>With a single-<a href="/facts/Execution_unit/uvg54JcX">execution-unit</a> processor, the best CPI attainable is 1. However, with a multiple-execution-unit processor, one may achieve even better CPI values (CPI < 1). In this case, the processor is said to be <i><a href="/facts/Superscalar/gPxRAb25">superscalar</a></i>. To get better CPI values without pipelining, the number of execution units must be greater than the number of stages. For example, with six executions units, six new instructions are fetched in stage 1 only after the six previous instructions finish at stage 5, therefore on average the number of clock cycles it takes to execute an instruction is 5/6 (CPI = 5/6 < 1). To get better CPI values with pipelining, there must be at least two execution units. For example, with two executions units, two new instructions are fetched every clock cycle by exploiting instruction-level parallelism, therefore two different instructions would complete stage 5 in every clock cycle and on average the number of clock cycles it takes to execute an instruction is 1/2 (CPI = 1/2 < 1).
</p>
<h2 id="examples">Examples</h2>
<h3>Example 1</h3>
<p>For the multi-cycle <a href="/facts/MIPS_architecture/efV4KgK4">MIPS</a>, there are five types of instructions:
</p>
<ul><li>Load (5 cycles)</li>
<li>Store (4 cycles)</li>
<li><a href="/facts/MIPS_architecture/efV4KgK4">R-type</a> (4 cycles)</li>
<li><a href="/facts/MIPS_architecture/efV4KgK4">Branch</a> (3 cycles)</li>
<li><a href="/facts/MIPS_architecture/efV4KgK4">Jump</a> (3 cycles)</li></ul>
<p>If a program has:
</p>
<ul><li>50% load instructions</li>
<li>25% store instructions</li>
<li>15% R-type instructions</li>
<li>8% branch instructions</li>
<li>2% jump instructions</li></ul>
<p>then, the CPI is:
</p><p>
  
    
      
        
          CPI
        
        =
        
          
            
              5
              ×
              50
              +
              4
              ×
              25
              +
              4
              ×
              15
              +
              3
              ×
              8
              +
              3
              ×
              2
            
            100
          
        
        =
        4.4
      
    
    {\displaystyle {\text{CPI}}={\frac {5\times 50+4\times 25+4\times 15+3\times 8+3\times 2}{100}}=4.4}

</p>
<h3>Example 2</h3>
<p><a class="footnote-ref" id="fnref:2" href="#fn:2"><sup>2</sup></a> A 400<a href="/facts/MHz/6Wshj5qm">MHz</a> processor was used to execute a <a href="/facts/Benchmark_program/XSS42cRe">benchmark program</a> with the following instruction mix and <a href="/facts/Clock_cycle/9UfTzGHx">clock cycle</a> count:
</p>
<table><tbody><tr><th>Instruction TYPE</th><th>Instruction count</th><th>Clock cycle count</th></tr><tr><td>Integer Arithmetic</td><td>45000</td><td>1</td></tr><tr><td>Data transfer</td><td>32000</td><td>2</td></tr><tr><td>Floating point</td><td>15000</td><td>2</td></tr><tr><td>Control transfer</td><td>8000</td><td>2</td></tr></tbody></table>
<p>Determine the effective CPI, <a href="/facts/Instructions_per_second/N23PAFGV">MIPS</a> (Millions of instructions per second) rate, and execution time for this program.
</p><p>
  
    
      
        
          CPI
        
        =
        
          
            
              45000
              ×
              1
              +
              32000
              ×
              2
              +
              15000
              ×
              2
              +
              8000
              ×
              2
            
            100000
          
        
        =
        
          
            155000
            100000
          
        
        =
        1.55
      
    
    {\displaystyle {\text{CPI}}={\frac {45000\times 1+32000\times 2+15000\times 2+8000\times 2}{100000}}={\frac {155000}{100000}}=1.55}

</p><p>
  
    
      
        400
        
        
          MHz
        
        =
        400
        ,
        000
        ,
        000
        
        
          Hz
        
      
    
    {\displaystyle 400\,{\text{MHz}}=400,000,000\,{\text{Hz}}}

</p><p>since: 
  
    
      
        
          MIPS
        
        ∝
        1
        
          /
        
        
          CPI
        
      
    
    {\displaystyle {\text{MIPS}}\propto 1/{\text{CPI}}}
  
 and 
  
    
      
        
          MIPS
        
        ∝
        
          clock frequency
        
      
    
    {\displaystyle {\text{MIPS}}\propto {\text{clock frequency}}}

</p><p>
  
    
      
        
          Effective processor performance
        
        =
        
          MIPS
        
        =
        
          
            clock frequency
            CPI
          
        
        ×
        
          
            1
            1 Million
          
        
      
    
    {\displaystyle {\text{Effective processor performance}}={\text{MIPS}}={\frac {\text{clock frequency}}{\text{CPI}}}\times {\frac {1}{\text{1 Million}}}}

=
        
          
            
              400
              ,
              000
              ,
              000
            
            
              1.55
              ×
              1000000
            
          
        
        =
        
          
            400
            1.55
          
        
        =
        258
        
        
          MIPS
        
      
    
    {\displaystyle ={\frac {400,000,000}{1.55\times 1000000}}={\frac {400}{1.55}}=258\,{\text{MIPS}}}

</p><p>Therefore:
</p><p>
  
    
      
        
          Execution time
        
        (
        T
        )
        =
        
          CPI
        
        ×
        
          Instruction count
        
        ×
        
          clock time
        
        =
        
          
            
              
                CPI
              
              ×
              
                Instruction Count
              
            
            frequency
          
        
      
    
    {\displaystyle {\text{Execution time}}(T)={\text{CPI}}\times {\text{Instruction count}}\times {\text{clock time}}={\frac {{\text{CPI}}\times {\text{Instruction Count}}}{\text{frequency}}}}

=
        
          
            
              1.55
              ×
              100000
            
            
              400
              ×
              1000000
            
          
        
        =
        
          
            1.55
            4000
          
        
        =
        0.0003875
        
        
          sec
        
        =
        0.3875
        
        
          ms
        
      
    
    {\displaystyle ={\frac {1.55\times 100000}{400\times 1000000}}={\frac {1.55}{4000}}=0.0003875\,{\text{sec}}=0.3875\,{\text{ms}}}

</p>
<h2 id="see-also">See also</h2>
<ul><li><a href="/facts/Cycle_per_second/WxtGGRFx">Cycle per second</a> (<a href="/facts/Hertz/6Wshj5qm">Hz</a>)</li>
<li><a href="/facts/Instructions_per_cycle/nHl8f6Ho">Instructions per cycle</a> (IPC)</li>
<li><a href="/facts/Instructions_per_second/N23PAFGV">Instructions per second</a> (IPS)</li>
<li><a href="/facts/Megahertz_myth/QxmaooRh">Megahertz myth</a></li>
<li><a href="/facts/Million_instructions_per_second/N23PAFGV">MIPS</a></li>
<li>The <a href="/facts/Benchmark_(computing)/XSS42cRe">benchmark</a> article provides a useful introduction to computer performance measurement for those readers interested in the topic.</li></ul>

<h2 id="references">References</h2>

<ol>
<li id="fn:1"><p>Patterson, David A.; Hennessy, John L. (1994). Computer Organization and Design: The Hardware/Software Interface. Morgan Kaufmann. ISBN 9781558602816. <a href="9781558602816" target="_blank">9781558602816</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li>
<li id="fn:2"><p>Advanced Computer Architecture by Kai Hwang, Chapter 1, Exercise Problem 1.1 <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li>
</ol>

Cycles per instruction open-in-new

Cycles per instruction