Memory cell (computing)

<h2 id="description">Description</h2>
The memory cell is the fundamental building block of memory. It can be implemented using different technologies, such as <a href="/facts/Bipolar_junction_transistor/9BMcGv5Q">bipolar</a>, <a href="/facts/MOSFET/eTDJT2Km">MOS</a>, and other <a href="/facts/Semiconductor_device/6W3ryr50">semiconductor devices</a>. It can also be built from <a href="/facts/Magnetism/eo75vApl">magnetic</a> material such as <a href="/facts/Ferrite_(magnet)/kBTM7Dqk">ferrite</a> cores or magnetic bubbles.<a class="footnote-ref" id="fnref:1" href="#fn:1">1</a> Regardless of the implementation technology used, the purpose of the binary memory cell is always the same. It stores one bit of binary information that can be accessed by reading the cell and it must be set to store a 1 and reset to store a 0.<a class="footnote-ref" id="fnref:2" href="#fn:2">2</a>

<h2 id="significance">Significance</h2>

Logic circuits without memory cells are called <a href="/facts/Combinational_logic/L1kaaVK5">combinational</a>, meaning the output depends only on the present input.
But memory is a key element of <a href="/facts/Digital_electronics/3kJcKbkw">digital systems</a>. In computers, it allows to store both programs and data and memory cells are also used for temporary storage of the output of combinational circuits to be used later by digital systems.
Logic circuits that use memory cells are called <a href="/facts/Sequential_logic/Rcs4thlu">sequential circuits</a>, meaning the output depends not only on the present input, but also on the history of past inputs.
This dependence on the history of past inputs makes these circuits <a href="/facts/State_(computer_science)/4Yu8xXHS">stateful</a> and it is the memory cells that store this state. 
These circuits require a timing generator or clock for their operation.<a class="footnote-ref" id="fnref:3" href="#fn:3">3</a>
Computer memory used in most contemporary <a href="/facts/Computer/SQe1aK05">computer systems</a> is built mainly out of DRAM cells; since the layout is much smaller than SRAM, it can be more densely packed yielding cheaper memory with greater capacity. Since the DRAM memory cell stores its value as the charge of a capacitor, and there are current leakage issues, its value must be constantly rewritten. This is one of the reasons that make DRAM cells slower than the larger SRAM (static RAM) cells, which has its value always available. That is the reason why SRAM memory is used for on-<a href="/facts/Integrated_circuit/fjn6vg7C">chip</a> <a href="/facts/CPU_cache/x8BYFcdv">cache</a> included in modern <a href="/facts/Microprocessor/Fx9CaQht">microprocessor</a> chips.<a class="footnote-ref" id="fnref:4" href="#fn:4">4</a>

<h2 id="history">History</h2>
Further information: <a href="/facts/Computer_memory/hQKVQ51J">Computer memory § History</a>

On December 11, 1946 <a href="/facts/Frederic_Calland_Williams/bzPnXzYa">Freddie Williams</a> applied for a patent on his cathode-ray tube (CRT) storing device (<a href="/facts/Williams_tube/6uXyju6I">Williams tube</a>) with 128 40-<a href="/facts/Bit/S972NSaD">bit</a> words. It was operational in 1947 and is considered the first practical implementation of <a href="/facts/Random-access_memory/DuD4bxh6">random-access memory</a> (RAM).<a class="footnote-ref" id="fnref:5" href="#fn:5">5</a> In that year, the first patent applications for <a href="/facts/Magnetic-core_memory/4TFIXSNd">magnetic-core memory</a> were filed by Frederick Viehe.<a class="footnote-ref" id="fnref:6" href="#fn:6">6</a><a class="footnote-ref" id="fnref:7" href="#fn:7">7</a> Practical magnetic-core memory was developed by <a href="/facts/An_Wang/CAtcP1ju">An Wang</a> in 1948, and improved by <a href="/facts/Jay_Wright_Forrester/z3bSVDjz">Jay Forrester</a> and <a href="/facts/Jan_A._Rajchman/SvI7DcXB">Jan A. Rajchman</a> in the early 1950s, before being commercialised with the <a href="/facts/Whirlwind_I/IbG8pxYt">Whirlwind</a> computer in 1953.<a class="footnote-ref" id="fnref:8" href="#fn:8">8</a> <a href="/facts/Ken_Olsen/0v0p1kYV">Ken Olsen</a> also contributed to its development.<a class="footnote-ref" id="fnref:9" href="#fn:9">9</a>
<a href="/facts/Semiconductor_memory/XXP0CacJ">Semiconductor memory</a> began in the early 1960s with bipolar memory cells, made of <a href="/facts/Bipolar_junction_transistor/9BMcGv5Q">bipolar transistors</a>. While it improved performance, it could not compete with the lower price of magnetic-core memory.<a class="footnote-ref" id="fnref:10" href="#fn:10">10</a>

<h3>MOS memory cells</h3>
Further information: <a href="/facts/Semiconductor_memory/XXP0CacJ">Semiconductor memory</a> and <a href="/facts/Random-access_memory/DuD4bxh6">Random-access memory § History</a>

In 1957, Frosch and Derick were able to manufacture the first silicon dioxide field effect transistors at Bell Labs, the first transistors in which drain and source were adjacent at the surface.<a class="footnote-ref" id="fnref:11" href="#fn:11">11</a> Subsequently, a team demonstrated a working <a href="/facts/MOSFET/eTDJT2Km">MOSFET</a> at Bell Labs 1960.<a class="footnote-ref" id="fnref:12" href="#fn:12">12</a><a class="footnote-ref" id="fnref:13" href="#fn:13">13</a> The invention of the MOSFET enabled the practical use of <a href="/facts/MOSFET/eTDJT2Km">metal–oxide–semiconductor</a> (MOS) transistors as memory cell storage elements, a function previously served by <a href="/facts/Magnetic-core_memory/4TFIXSNd">magnetic cores</a>.<a class="footnote-ref" id="fnref:14" href="#fn:14">14</a>
The first modern memory cells were introduced in 1964, when John Schmidt designed the first 64-bit p-channel MOS (<a href="/facts/PMOS_logic/DWmuIrcn">PMOS</a>) <a href="/facts/Static_random-access_memory/Pmyo4V5e">static random-access memory</a> (SRAM).<a class="footnote-ref" id="fnref:15" href="#fn:15">15</a><a class="footnote-ref" id="fnref:16" href="#fn:16">16</a>
SRAM typically has six-<a href="/facts/Transistor/Bmr8zwL0">transistor</a> cells, whereas <a href="/facts/Dynamic_random-access_memory/koI9FGo5">DRAM</a> (dynamic random-access memory) typically has single-transistor cells.<a class="footnote-ref" id="fnref:17" href="#fn:17">17</a><a class="footnote-ref" id="fnref:18" href="#fn:18">18</a> In 1965, <a href="/facts/Toshiba/QHRaw8Tr">Toshiba</a>'s Toscal BC-1411 <a href="/facts/Calculator/eeLfRS8L">electronic calculator</a> used a form of capacitive bipolar DRAM, storing 180-bit data on discrete memory cells, consisting of <a href="/facts/Germanium/wtoALHGs">germanium</a> bipolar transistors and capacitors.<a class="footnote-ref" id="fnref:19" href="#fn:19">19</a><a class="footnote-ref" id="fnref:20" href="#fn:20">20</a> MOS technology is the basis for modern DRAM. In 1966, <a href="/facts/Robert_H._Dennard/ehvGFrmD">Robert H. Dennard</a> at the <a href="/facts/Thomas_J._Watson_Research_Center/XfGnAzRW">IBM Thomas J. Watson Research Center</a> was working on MOS memory. While examining the characteristics of MOS technology, he found it was capable of building <a href="/facts/Capacitor/hyowqv7n">capacitors</a>, and that storing a charge or no charge on the MOS capacitor could represent the 1 and 0 of a bit, while the MOS transistor could control writing the charge to the capacitor. This led to his development of a single-transistor DRAM memory cell.<a class="footnote-ref" id="fnref:21" href="#fn:21">21</a> In 1967, Dennard filed a patent for a single-transistor DRAM memory cell, based on MOS technology.<a class="footnote-ref" id="fnref:22" href="#fn:22">22</a>
The first commercial bipolar 64-bit <a href="/facts/Static_random-access_memory/Pmyo4V5e">SRAM</a> was released by <a href="/facts/Intel/SMF0gJJX">Intel</a> in 1969 with the 3101 <a href="/facts/Schottky_transistor/w8tjjAlJ">Schottky</a> <a href="/facts/Transistor%25E2%2580%2593transistor_logic/z4bvHotl">TTL</a>. One year later, it released the first DRAM <a href="/facts/Integrated_circuit/fjn6vg7C">integrated circuit</a> chip, the <a href="/facts/Intel_1103/yrfRI7jS">Intel 1103</a>, based on MOS technology. By 1972, it beat previous records in <a href="/facts/Semiconductor_memory/XXP0CacJ">semiconductor memory</a> sales.<a class="footnote-ref" id="fnref:23" href="#fn:23">23</a> DRAM chips during the early 1970s had three-transistor cells, before single-transistor cells became standard since the mid-1970s.<a class="footnote-ref" id="fnref:24" href="#fn:24">24</a><a class="footnote-ref" id="fnref:25" href="#fn:25">25</a>
<a href="/facts/CMOS/NJIWYgBl">CMOS</a> memory was commercialized by <a href="/facts/RCA/NWyjNN6R">RCA</a>, which launched a 288-bit CMOS SRAM memory chip in 1968.<a class="footnote-ref" id="fnref:26" href="#fn:26">26</a> CMOS memory was initially slower than <a href="/facts/NMOS_logic/6hup3T21">NMOS</a> memory, which was more widely used by computers in the 1970s.<a class="footnote-ref" id="fnref:27" href="#fn:27">27</a> In 1978, <a href="/facts/Hitachi/KeK38e82">Hitachi</a> introduced the twin-well CMOS process, with its HM6147 (4 kb SRAM) memory chip, manufactured with a <a href="/facts/3_%25CE%25BCm_process/C0CxqFTf">3 μm process</a>. The HM6147 chip was able to match the performance of the fastest NMOS memory chip at the time, while the HM6147 also consumed significantly less power. With comparable performance and much less power consumption, the twin-well CMOS process eventually overtook NMOS as the most common <a href="/facts/Semiconductor_device_fabrication/Jd23Mu1z">semiconductor manufacturing process</a> for computer memory in the 1980s.<a class="footnote-ref" id="fnref:28" href="#fn:28">28</a>
The two most common types of DRAM memory cells since the 1980s have been trench-capacitor cells and stacked-capacitor cells.<a class="footnote-ref" id="fnref:29" href="#fn:29">29</a> Trench-capacitor cells are where holes (trenches) are made in a silicon substrate, whose side walls are used as a memory cell, whereas 
stacked-capacitor cells are the earliest form of three-dimensional memory (3D memory), where memory cells are stacked vertically in a three-dimensional cell structure.<a class="footnote-ref" id="fnref:30" href="#fn:30">30</a> Both debuted in 1984, when Hitachi introduced trench-capacitor memory and <a href="/facts/Fujitsu/6e5gvNSa">Fujitsu</a> introduced stacked-capacitor memory.<a class="footnote-ref" id="fnref:31" href="#fn:31">31</a>

<h3>Floating-gate MOS memory cells</h3>
See also: <a href="/facts/Floating-gate_MOSFET/AvmK0oBb">Floating-gate MOSFET</a> and <a href="/facts/Nonvolatile_memory/EN72wMD9">Nonvolatile memory</a>
The <a href="/facts/Floating-gate_MOSFET/AvmK0oBb">floating-gate MOSFET</a> (FGMOS) was invented by <a href="/facts/Dawon_Kahng/Lpo06Q3w">Dawon Kahng</a> and <a href="/facts/Simon_Sze/K1pL9Eo0">Simon Sze</a> at <a href="/facts/Bell_Labs/fKP5Gk0H">Bell Labs</a> in 1967.<a class="footnote-ref" id="fnref:32" href="#fn:32">32</a> They proposed the concept of floating-gate memory cells, using FGMOS transistors, which could be used to produce <a href="/facts/EPROM/kXcEca36">reprogrammable ROM</a> (read-only memory).<a class="footnote-ref" id="fnref:33" href="#fn:33">33</a> Floating-gate memory cells later became the basis for <a href="/facts/Non-volatile_memory/EN72wMD9">non-volatile memory</a> (NVM) technologies including <a href="/facts/EPROM/kXcEca36">EPROM</a> (erasable programmable ROM), <a href="/facts/EEPROM/0yAMFY0I">EEPROM</a> (electrically erasable programmable ROM) and <a href="/facts/Flash_memory/Cn8JsStx">flash memory</a>.<a class="footnote-ref" id="fnref:34" href="#fn:34">34</a>
Flash memory was invented by <a href="/facts/Fujio_Masuoka/ucE5pk8W">Fujio Masuoka</a> at <a href="/facts/Toshiba/QHRaw8Tr">Toshiba</a> in 1980.<a class="footnote-ref" id="fnref:35" href="#fn:35">35</a><a class="footnote-ref" id="fnref:36" href="#fn:36">36</a> Masuoka and his colleagues presented the invention of <a href="/facts/NOR_flash/Cn8JsStx">NOR flash</a> in 1984,<a class="footnote-ref" id="fnref:37" href="#fn:37">37</a> and then <a href="/facts/NAND_flash/Cn8JsStx">NAND flash</a> in 1987.<a class="footnote-ref" id="fnref:38" href="#fn:38">38</a> <a href="/facts/Multi-level_cell/nBqK3614">Multi-level cell</a> (MLC) flash memory was introduced by <a href="/facts/NEC/YnlUsMBA">NEC</a>, which demonstrated <a href="/facts/Multi-level_cell/nBqK3614">quad-level cells</a> in a 64 <a href="/facts/Mebibit/sbVr3xfY">Mb</a> flash chip storing 2-bit per cell in 1996.<a class="footnote-ref" id="fnref:39" href="#fn:39">39</a> 3D <a href="/facts/V-NAND/Cn8JsStx">V-NAND</a>, where flash memory cells are stacked vertically using 3D <a href="/facts/Charge_trap_flash/0ccI1IFJ">charge trap flash</a> (CTP) technology, was first announced by Toshiba in 2007,<a class="footnote-ref" id="fnref:40" href="#fn:40">40</a> and first commercially manufactured by <a href="/facts/Samsung_Electronics/STxnmHwl">Samsung Electronics</a> in 2013.<a class="footnote-ref" id="fnref:41" href="#fn:41">41</a><a class="footnote-ref" id="fnref:42" href="#fn:42">42</a>

<h2 id="implementation">Implementation</h2>
The following schematics detail the three most used implementations for memory cells: 

<ul><li>The dynamic random access memory cell (DRAM);</li>
<li>The static random access memory cell (SRAM);</li>
<li>Flip-flops like the J/K shown below, using only <a href="/facts/Logic_gate/RHLulvKI">logic gates</a>.</li></ul>
<table><tbody><tr><td></td><td></td><td></td></tr></tbody></table>
<h2 id="operation">Operation</h2>
<h3>DRAM memory cell</h3>

<h4>Storage</h4>
The storage element of the <a href="/facts/Dynamic_random-access_memory/koI9FGo5">DRAM</a> memory cell is the <a href="/facts/Capacitor/hyowqv7n">capacitor</a> labeled (4) in the diagram above. The charge stored in the capacitor degrades over time, so its value must be refreshed (read and rewritten) periodically. The <a href="/facts/MOSFET/eTDJT2Km">nMOS</a> transistor (3) acts as a gate to allow reading or writing when open or storing when closed.<a class="footnote-ref" id="fnref:43" href="#fn:43">43</a>
<h4>Reading</h4>
For reading the Word line (2) drives a logic 1 (voltage high) into the gate of the <a href="/facts/MOSFET/eTDJT2Km">nMOS</a> transistor (3) which makes it conductive and the charge stored at the capacitor (4) is then transferred to the bit line (1). The bit line will have a <a href="/facts/Parasitic_capacitance/xNHYvmoo">parasitic capacitance</a> (5) that will drain part of the charge and slow the reading process. The capacitance of the bit line will determine the needed size of the storage capacitor (4). It is a trade-off. If the storage capacitor is too small, the voltage of the bit line would take too much time to raise or not even rise above the threshold needed by the amplifiers at the end of the bit line. Since the reading process degrades the charge in the storage capacitor (4) its value is rewritten after each read.<a class="footnote-ref" id="fnref:44" href="#fn:44">44</a>
<h4>Writing</h4>
The writing process is the easiest, the desired value logic 1 (high voltage) or logic 0 (low voltage) is driven into the bit line. The word line activates the <a href="/facts/MOSFET/eTDJT2Km">nMOS</a> transistor (3) connecting it to the storage capacitor (4). The only issue is to keep it open enough time to ensure that the capacitor is fully charged or discharged before turning off the nMOS transistor (3).<a class="footnote-ref" id="fnref:45" href="#fn:45">45</a>
<h3>SRAM memory cell</h3>

<h4>Storage</h4>
The working principle of <a href="/facts/Static_random-access_memory/Pmyo4V5e">SRAM</a> memory cell can be easier to understand if the transistors M1 through M4 are drawn as <a href="/facts/Logic_gate/RHLulvKI">logic gates</a>. That way it is clear that at its heart, the cell storage is built by using two cross-coupled <a href="/facts/Inverter_(logic_gate)/pGk3qGTI">inverters</a>. This simple loop creates a bi-stable circuit. A logic 1 at the input of the first inverter turns into a 0 at its output, and it is fed into the second inverter which transforms that logic 0 back to a logic 1 feeding back the same value to the input of the first inverter. That creates a stable state that does not change over time. Similarly the other stable state of the circuit is to have a logic 0 at the input of the first inverter. After being inverted twice it will also feedback the same value.<a class="footnote-ref" id="fnref:46" href="#fn:46">46</a>
Therefore there are only two stable states that the circuit can be in:
<ul><li>
 
 
 
 
 Q
 
 
 
 {\displaystyle \scriptstyle Q}
 
 = 0 and   
 
 
 
 
 
 
 Q
 ¯
 
 
 
 
 
 {\displaystyle \scriptstyle {\overline {Q}}}
 
 = 1</li>
<li>
 
 
 
 
 Q
 
 
 
 {\displaystyle \scriptstyle Q}
 
 = 1 and   
 
 
 
 
 
 
 Q
 ¯
 
 
 
 
 
 {\displaystyle \scriptstyle {\overline {Q}}}
 
 = 0</li></ul>
<h4>Reading</h4>
To read the contents of the memory cell stored in the loop, the transistors M5 and M6 must be turned on. when they receive voltage to their gates from the word line (
 
 
 
 
 W
 L
 
 
 
 {\displaystyle \scriptstyle WL}
 
), they become conductive and so the 
 
 
 
 
 Q
 
 
 
 {\displaystyle \scriptstyle Q}
 
 and  
 
 
 
 
 
 
 Q
 ¯
 
 
 
 
 
 {\displaystyle \scriptstyle {\overline {Q}}}
 
  values get transmitted to the bit line (
 
 
 
 
 B
 L
 
 
 
 {\displaystyle \scriptstyle BL}
 
) and to its complement (
 
 
 
 
 
 
 
 B
 L
 
 ¯
 
 
 
 
 
 {\displaystyle \scriptstyle {\overline {BL}}}
 
).<a class="footnote-ref" id="fnref:47" href="#fn:47">47</a> Finally this values get amplified at the end of the bit lines.<a class="footnote-ref" id="fnref:48" href="#fn:48">48</a>
<h4>Writing</h4>
The writing process is similar, the difference is that now the new value that will be stored in the memory cell is driven into the bit line (
 
 
 
 
 B
 L
 
 
 
 {\displaystyle \scriptstyle BL}
 
) and the inverted one into its complement (
 
 
 
 
 
 
 
 B
 L
 
 ¯
 
 
 
 
 
 {\displaystyle \scriptstyle {\overline {BL}}}
 
). Next transistors M5 and M6 are open by driving a logic 1 (voltage high) into the word line (
 
 
 
 
 W
 L
 
 
 
 {\displaystyle \scriptstyle WL}
 
). This effectively connects the bit lines to the by-stable inverter loop. There are two possible cases:
<ol><li>If the value of the loop is the same as the new value driven, there is no change;</li>
<li>if the value of the loop is different from the new value driven there are two conflicting values, in order for the voltage in the bit lines to overwrite the output of the inverters, the size of the M5 and M6 transistors must be larger than that of the M1-M4 transistors. This allows more current to flow through first ones and therefore tips the voltage in the direction of the new value, at some point the loop will then amplify this intermediate value to full rail.<a class="footnote-ref" id="fnref:49" href="#fn:49">49</a></li></ol>
<h3>Flip-flop</h3>
Main article: <a href="/facts/Flip-flop_(electronics)/vA99xjM7">Flip-flop (electronics)</a>
The <a href="/facts/Flip-flop_(electronics)/vA99xjM7">flip-flop</a> has many different implementations, its storage element is usually a latch consisting of a <a href="/facts/NAND_gate/g6FUuhJT">NAND gate</a> loop or a <a href="/facts/NOR_gate/3l3MqaMI">NOR gate</a> loop with additional gates used to implement clocking. Its value is always available for reading as an output. The value remains stored until it is changed through the set or reset process. Flip-flops are typically implemented using <a href="/facts/MOSFET/eTDJT2Km">MOSFETs</a>.

<h3>Floating gate</h3>

See also: <a href="/facts/Floating-gate_MOSFET/AvmK0oBb">Floating-gate MOSFET</a> and <a href="/facts/Charge_trap_flash/0ccI1IFJ">Charge trap flash</a>
<a href="/facts/Floating-gate_MOSFET/AvmK0oBb">Floating-gate</a> memory cells, based on <a href="/facts/Floating-gate_MOSFET/AvmK0oBb">floating-gate MOSFETs</a>, are used for most <a href="/facts/Non-volatile_memory/EN72wMD9">non-volatile memory</a> (NVM) technologies, including <a href="/facts/EPROM/kXcEca36">EPROM</a>, <a href="/facts/EEPROM/0yAMFY0I">EEPROM</a> and <a href="/facts/Flash_memory/Cn8JsStx">flash memory</a>.<a class="footnote-ref" id="fnref:50" href="#fn:50">50</a> According to R. Bez and A. Pirovano:

<blockquote>A floating-gate memory cell is basically an <a href="/facts/MOSFET/eTDJT2Km">MOS</a> transistor with a gate completely surrounded by <a href="/facts/Dielectrics/PnVt9P2G">dielectrics</a> (Fig. 1.2), the floating-gate (FG), and electrically governed by a capacitive-coupled control-gate (CG). Being electrically isolated, the FG acts as the storing electrode for the cell device. Charge injected into the FG is maintained there, allowing modulation of the ‘apparent’ threshold voltage (i.e. VT seen from the CG) of the cell transistor.<a class="footnote-ref" id="fnref:51" href="#fn:51">51</a></blockquote>
<h2 id="see-also">See also</h2>
<ul><li><a href="/facts/Dynamic_random-access_memory/koI9FGo5">Dynamic random-access memory</a></li>
<li><a href="/facts/Flip-flop_(electronics)/vA99xjM7">Flip-flop (electronics)</a></li>
<li><a href="/facts/Row_hammer/XCaHA39b">Row hammer</a></li>
<li><a href="/facts/Static_random-access_memory/Pmyo4V5e">Static random-access memory</a></li></ul>

<h2 id="references">References</h2>

<ol>
<li id="fn:1">D. Tang, Denny; Lee, Yuan-Jen (2010). Magnetic memory: Fundamentals and technology. Cambridge University Press. p. 91. ISBN 978-1139484497. Retrieved 13 December 2015. <a href="978-1139484497" target="_blank">978-1139484497</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></li>
<li id="fn:2">Fletcher, William (1980). An engineering approach to digital design. Prentice-Hall. p. 283. ISBN 0-13-277699-5. <a href="0-13-277699-5" target="_blank">0-13-277699-5</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></li>
<li id="fn:3">Microelectronic circuits (Second ed.). Holt, Rinehart and Winston, Inc. 1987. p. 883. ISBN 0-03-007328-6. <a href="0-03-007328-6" target="_blank">0-03-007328-6</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></li>
<li id="fn:4">"The technical question: the cache, how does it work?". PC World Fr (in French). Archived from the original on 30 March 2014. <a href="https://web.archive.org/web/20140330034345/http://www.pcworld.fr/materiel/actualites,lqt-cache-cpu-memoire-cache-sram,547751,1.htm" target="_blank">https://web.archive.org/web/20140330034345/http://www.pcworld.fr/materiel/actualites,lqt-cache-cpu-memoire-cache-sram,547751,1.htm</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></li>
<li id="fn:5">O’Regan, Gerard (2013). Giants of computing: A compendium of select, pivotal pioneers. Springer. p. 267. ISBN 978-1447153405. Retrieved 13 December 2015. <a href="978-1447153405" target="_blank">978-1447153405</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></li>
<li id="fn:6">Reilly, Edwin D. (2003). Milestones in computer science and information technology. Greenwood publishing group. p. 164. ISBN 9781573565219. <a href="9781573565219" target="_blank">9781573565219</a> <a href="#fnref:6" class="footnote-back-ref">↩</a></li>
<li id="fn:7">W. Pugh, Emerson; R. Johnson, Lyle; H. Palmer, John (1991). IBM's 360 and early 370 systems. MIT Press. p. 706. ISBN 0262161230. Retrieved 9 December 2015. <a href="0262161230" target="_blank">0262161230</a> <a href="#fnref:7" class="footnote-back-ref">↩</a></li>
<li id="fn:8">"1953: Whirlwind computer debuts core memory". Computer History Museum. Retrieved 2 August 2019. <a href="https://www.computerhistory.org/storageengine/whirlwind-computer-debuts-core-memory/" target="_blank">https://www.computerhistory.org/storageengine/whirlwind-computer-debuts-core-memory/</a> <a href="#fnref:8" class="footnote-back-ref">↩</a></li>
<li id="fn:9">Taylor, Alan (18 June 1979). Computerworld: Mass. Town has become computer capital. IDG Enterprise. p. 25. <a href="https://books.google.com/books?id=rfsvbXyn0ZEC&q=jay+forrester&pg=PA25" target="_blank">https://books.google.com/books?id=rfsvbXyn0ZEC&q=jay+forrester&pg=PA25</a> <a href="#fnref:9" class="footnote-back-ref">↩</a></li>
<li id="fn:10">"1966: Semiconductor RAMs serve high-speed storage needs". Computer History Museum. Retrieved 19 June 2019. <a href="https://www.computerhistory.org/siliconengine/semiconductor-rams-serve-high-speed-storage-needs/" target="_blank">https://www.computerhistory.org/siliconengine/semiconductor-rams-serve-high-speed-storage-needs/</a> <a href="#fnref:10" class="footnote-back-ref">↩</a></li>
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<li id="fn:18">"1970: Semiconductors compete with magnetic cores". Computer history museum. Retrieved 19 June 2019. <a href="https://www.computerhistory.org/storageengine/semiconductors-compete-with-magnetic-cores/" target="_blank">https://www.computerhistory.org/storageengine/semiconductors-compete-with-magnetic-cores/</a> <a href="#fnref:18" class="footnote-back-ref">↩</a></li>
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<li id="fn:20">"Toshiba "Toscal" BC-1411 desktop calculator". Archived from the original on 20 May 2007. <a href="https://web.archive.org/web/20070520202433/http://www.oldcalculatormuseum.com/toshbc1411.html" target="_blank">https://web.archive.org/web/20070520202433/http://www.oldcalculatormuseum.com/toshbc1411.html</a> <a href="#fnref:20" class="footnote-back-ref">↩</a></li>
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<li id="fn:23">Kent, Allen; Williams, James G. (6 January 1992). Encyclopedia of microcomputers: volume 9 - Icon programming language to knowledge-based systems: APL techniques. CRC press. p. 131. ISBN 9780824727086. <a href="9780824727086" target="_blank">9780824727086</a> <a href="#fnref:23" class="footnote-back-ref">↩</a></li>
<li id="fn:24">"Late 1960s: Beginnings of MOS memory" (PDF). Semiconductor history museum of Japan. 23 January 2019. Retrieved 27 June 2019. <a href="http://www.shmj.or.jp/english/pdf/ic/exhibi718E.pdf" target="_blank">http://www.shmj.or.jp/english/pdf/ic/exhibi718E.pdf</a> <a href="#fnref:24" class="footnote-back-ref">↩</a></li>
<li id="fn:25">"1970: Semiconductors compete with magnetic cores". Computer history museum. Retrieved 19 June 2019. <a href="https://www.computerhistory.org/storageengine/semiconductors-compete-with-magnetic-cores/" target="_blank">https://www.computerhistory.org/storageengine/semiconductors-compete-with-magnetic-cores/</a> <a href="#fnref:25" class="footnote-back-ref">↩</a></li>
<li id="fn:26">"1963: Complementary MOS circuit configuration is invented". Computer history museum. Retrieved 6 July 2019. <a href="https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/" target="_blank">https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/</a> <a href="#fnref:26" class="footnote-back-ref">↩</a></li>
<li id="fn:27">"1978: Double-well fast CMOS SRAM (Hitachi)" (PDF). Semiconductor history museum of Japan. Archived (PDF) from the original on 5 July 2019. Retrieved 5 July 2019. <a href="http://www.shmj.or.jp/english/pdf/ic/exhibi727E.pdf" target="_blank">http://www.shmj.or.jp/english/pdf/ic/exhibi727E.pdf</a> <a href="#fnref:27" class="footnote-back-ref">↩</a></li>
<li id="fn:28">"1978: Double-well fast CMOS SRAM (Hitachi)" (PDF). Semiconductor history museum of Japan. Archived (PDF) from the original on 5 July 2019. Retrieved 5 July 2019. <a href="http://www.shmj.or.jp/english/pdf/ic/exhibi727E.pdf" target="_blank">http://www.shmj.or.jp/english/pdf/ic/exhibi727E.pdf</a> <a href="#fnref:28" class="footnote-back-ref">↩</a></li>
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<li id="fn:48">Li, Hai; Chen, Yiran (19 April 2016). Nonvolatile memory design: Magnetic, resistive, and phase change. CRC press. pp. 6, 7. ISBN 9781439807460. <a href="9781439807460" target="_blank">9781439807460</a> <a href="#fnref:48" class="footnote-back-ref">↩</a></li>
<li id="fn:49">Li, Hai; Chen, Yiran (19 April 2016). Nonvolatile memory design: Magnetic, resistive, and phase change. CRC press. pp. 6, 7. ISBN 9781439807460. <a href="9781439807460" target="_blank">9781439807460</a> <a href="#fnref:49" class="footnote-back-ref">↩</a></li>
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<li id="fn:51">Bez, R.; Pirovano, A. (2019). Advances in non-volatile memory and storage technology. Woodhead Publishing. ISBN 9780081025857. <a href="9780081025857" target="_blank">9780081025857</a> <a href="#fnref:51" class="footnote-back-ref">↩</a></li>
</ol>

Memory cell (computing) open-in-new

Memory cell (computing)