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Centaur Technology
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<h2 id="history">History</h2> <p>Centaur Technologies Inc. was founded in April 1995 by <a href="/facts/Glenn_Henry_(IT_entrepreneur)/VIKkzk50">Glenn Henry</a>, Terry Parks, Darius Gaskins, and Al Sato. The funding was provided by <a href="/facts/Integrated_Device_Technology/vuXjhG5H">Integrated Device Technology</a>, Inc (IDT). The business goal was to develop compatible <a href="/facts/X86/Kypq5fgu">x86</a> processors that were less expensive than <a href="/facts/Intel/SMF0gJJX">Intel</a> processors and consumed less power. There were two main elements of the plan: </p> <ol><li>a new design, developed from scratch, of an x86 processor core optimized differently from Intel's cores;</li> <li>a novel management approach designed to achieve high productivity.</li></ol> <p>While funded by IDT, three different Centaur designs were shipped under the marketing name of <a href="/facts/WinChip/mslaY86X">WinChip</a>. In September 1999, Centaur was purchased from IDT by <a href="/facts/VIA_Technologies/g6REHNFE">VIA Technologies</a>, a Taiwanese company. Since then, five designs have shipped with the marketing name of <a href="/facts/VIA_C3/Y4IQ8VCd">VIA C3</a>, as well as a number of designs for the <a href="/facts/VIA_C7/a4nqwGyr">VIA C7</a> processor and their latest 64-bit CPU, the <a href="/facts/VIA_Nano/82nYJeBy">VIA Nano</a>. </p><p>The VIA Nano design has been further refined and improved in chips produced by <a href="/facts/Zhaoxin/2wpVktlp">Zhaoxin</a> (a VIA <a href="/facts/Joint_venture_company/f2Fv8QqA">joint venture company</a>). </p><p>In late 2019, Centaur announced the "World’s First High-Performance x86 SoC with Integrated AI Coprocessor", the CNS core.<a class="footnote-ref" id="fnref:3" href="#fn:3"><sup>3</sup></a> </p><p>In November 2021, Intel recruited the majority of the employees of the Centaur Technology division from VIA, a deal worth $125 million, effectively acquiring the talent and know-how of the x86 division.<a class="footnote-ref" id="fnref:4" href="#fn:4"><sup>4</sup></a><a class="footnote-ref" id="fnref:5" href="#fn:5"><sup>5</sup></a> VIA retained the x86 licence and associated patents, and its Zhaoxin CPU joint-venture continues.<a class="footnote-ref" id="fnref:6" href="#fn:6"><sup>6</sup></a> </p> <h2 id="design-methodology">Design methodology</h2> <p>Centaur's chips historically have been much smaller than comparable x86 designs at their time, and they are thus cheaper to manufacture and consume less power . This made them attractive in the <a href="/facts/Embedded_processor/a4muX1wU">embedded</a> marketplace. </p><p>Centaur's design philosophy was always centered on "sufficient" performance for tasks that its target market demands. Some of the design trade-offs made by the design team ran contrary to accepted wisdom. </p><p>Centaur/VIA was among the first to design processors with hardware encryption, hash and random number acceleration in the form of <a href="/facts/VIA_PadLock/GtR3rG4z">VIA PadLock</a>, starting with a 2004 VIA C7 release. Around the same time <a href="/facts/Geode_(processor)/uIL9401N">NSC Geode LX</a> added support for <a href="/facts/Advanced_Encryption_Standard/HdXGBY2Q">AES128</a>. In 2008 Intel and AMD followed up with specifications <a href="/facts/AES_instruction_set/NomFEB4w">AES-NI</a>, <a href="/facts/Intel_SHA_extensions/qDzy2N70">Intel SHA extensions</a> in 2013, and <a href="/facts/RDRAND/IdeN4y36">RDRAND</a> in 2015. </p> <h3>VIA C3</h3> <p class="note">Main article: <a href="/facts/VIA_C3/Y4IQ8VCd">VIA C3</a></p> <ul><li>Because memory performance is the limiting factor in many benchmarks, VIA processors implement large <a href="/facts/CPU_cache/x8BYFcdv">primary caches</a>, large <a href="/facts/Translation_Lookaside_Buffer/vvwGkfvD">TLBs</a>, and aggressive <a href="/facts/Instruction_prefetch/cuCGl0Vm">prefetching</a>, among other enhancements. While these features are not unique to VIA, memory access optimization is one area where features were not sacrificed to save die space. In fact, generous primary caches (128KB) have always been a distinctive hallmark of Centaur designs.</li> <li>Generally, clock frequency is favored over increasing instructions per cycle. Complex features such as out-of-order instruction execution are deliberately not implemented, because they impact the ability to increase the clock rate, require a lot of extra die space and power, and have little impact on performance in several common application scenarios.</li> <li>The pipeline is arranged to provide one-clock execution of the heavily used register–memory and memory–register forms of x86 instructions. Several frequently used instructions require fewer clock cycles than on other x86 processors.</li> <li>Rarely used x86 instructions are implemented in <a href="/facts/Microcode/XQEsr2X3">microcode</a> and emulated as combinations of other x86 instructions. This saves die space and contributes to low power consumption. The impact on the majority of real-world application scenarios is minimal.</li> <li>These design principles are derivative from the original <a href="/facts/RISC/aQbGM62p">RISC</a> advocates, who claim that a smaller set of instructions, better optimized, can deliver faster overall CPU performance. The C3 design cannot be considered a pure RISC design because it accepts the x86 instruction set which is a <a href="/facts/Complex_instruction_set_computer/Ucvyh2xq">CISC</a> design.</li> <li>In addition to x86, these processors support the undocumented <a href="/facts/Alternate_Instruction_Set/oEgD3PFV">Alternate Instruction Set</a>.</li></ul> <h3>VIA C7</h3> <p class="note">Main article: <a href="/facts/VIA_C7/a4nqwGyr">VIA C7</a></p> <ul><li>VIA C7 Esther (C5J) as an evolutionary step after VIA C3 Nehemiah+ (C5P), in which Centaur followed their traditional approach of balancing performance against a constrained transistor/power budget.</li> <li>The cornerstone of the VIA C3 series chips' design philosophy has been that even a relatively simple in-order scalar core can offer reasonable performance against a complex superscalar out-of-order core if supported by an efficient "front-end", i.e. prefetch, cache and branch prediction mechanisms.</li> <li>In the case of VIA C7, the design team focused on further streamlining the "front-end" of the chip, i.e. cache size, associativity and throughput as well as the prefetch system.<a class="footnote-ref" id="fnref:7" href="#fn:7"><sup>7</sup></a> At the same time, no significant changes to the execution core ("back-end") of the chip seem to have been made.</li> <li>The VIA C7 successfully further closes the gap in performance with AMD/Intel chips, since clock speed is not thermally constrained.</li></ul> <h3>VIA Nano</h3> <p class="note">Main article: <a href="/facts/VIA_Nano/82nYJeBy">VIA Nano</a></p> <ul><li>VIA Nano Isaiah (CN) is a combination of a number of firsts from Centaur, including their first superscalar out-of-order CPU and their first 64-bit CPU.</li> <li>The development of the VIA Nano focused on radically improving the performance side of the performance-per-watt equation while still maintaining a similar <a href="/facts/Thermal_design_power/Idcy26tM">TDP</a> to the VIA C7.</li></ul> <h3>CNS core</h3> <p>Centaur announced a new x86-64 "CNS" CPU with <a href="/facts/AVX-512/2KpGqI8t">AVX-512</a> support and integrated AI coprocessor in late 2019.<a class="footnote-ref" id="fnref:8" href="#fn:8"><sup>8</sup></a> The CNS CPU was cancelled in 2021 when VIA sold parts of its Centaur division to Intel.<a class="footnote-ref" id="fnref:9" href="#fn:9"><sup>9</sup></a> The CNS core CPUs had up to 8 cores and ran at a 2 GHz base frequency. It used the same LGA2011 pin socket as Intel's LGA2011-3 CPUs, however it is not electrically compatible with Intel motherboards. The CNS CPU cores were made on the TSMC 16 nm node. Some of the advancements made on CNS were later used in some <a href="/facts/Zhaoxin/2wpVktlp">Zhaoxin</a> Semiconductor CPUs in which VIA is in a joint venture with.<a class="footnote-ref" id="fnref:10" href="#fn:10"><sup>10</sup></a> </p> <h3>Comparative die size</h3> <table><tbody><tr><th>Processor</th><th>Secondarycache (k)</th><th>Die size130 nm (mm²)</th><th>Die size90 nm (mm²)</th><th>Die size65 nm (mm²)</th></tr><tr><th>VIA Nano 1000/2000</th><td>1024</td><td>N/A</td><td>N/A</td><td>63.3</td></tr><tr><th>VIA C3 / VIA C7</th><td>64/128</td><td>52</td><td>30</td><td>N/A</td></tr><tr><th>Athlon XP</th><td>256</td><td>84</td><td>N/A</td><td>N/A</td></tr><tr><th>Athlon 64</th><td>512</td><td>144</td><td>84</td><td>77</td></tr><tr><th>Pentium M</th><td>2048</td><td>N/A</td><td>84</td><td>N/A</td></tr><tr><th>P4 Northwood</th><td>512</td><td>146</td><td>N/A</td><td>N/A</td></tr><tr><th>P4 Prescott</th><td>1024</td><td>N/A</td><td>110</td><td>N/A</td></tr></tbody></table> <p>Note: Even the 180 nm <a href="/facts/Duron/V1Ny0C5n">Duron</a> Morgan core (106 mm²) with a 64K <a href="/facts/Secondary_cache/x8BYFcdv">secondary cache</a>, when shrunk down to a 130 nm process, would have still had a die size of 76 mm². The VIA x86 core is smaller and cheaper to produce. As can be seen in this table, almost four C7 cores could be manufactured in the same area as a one-<a href="/facts/Pentium_4/6tIFuHIF">P4 Prescott</a> core on 90 nm process. </p> <h2 id="see-also">See also</h2> <ul><li><a href="/facts/Zhaoxin/2wpVktlp">Zhaoxin</a></li></ul> <h2 id="external-links">External links</h2> <ul><li><a href="https://web.archive.org/web/19981111184838/http://www.centtech.com/">Home page</a>[<i>usurped</i>]</li> <li><a href="http://www.cognitivefilms.com/rise-of-the-centaur/">Rise of the Centaur (2015) - Documentary Film</a></li></ul> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>Coots, Carson (2015-11-01), Rise of the Centaur (Documentary), John Carls, Darius Gaskins, Suresh Hariharan, Cognitive Films, retrieved 2024-05-01 <a href="https://www.imdb.com/title/tt5690958/" target="_blank">https://www.imdb.com/title/tt5690958/</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>Shilov, Anton (December 29, 2021). "Via Shutters Centaur Technology Site, Sells Off Equipment". Tom's Hardware. Retrieved March 28, 2023. <a href="https://www.tomshardware.com/news/via-sells-off-equipment-from-centaur-preps-to-shut-down-site" target="_blank">https://www.tomshardware.com/news/via-sells-off-equipment-from-centaur-preps-to-shut-down-site</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li> <li id="fn:3"><p>"Centaur Unveils Its New Server-Class x86 Core: CNS; Adds AVX-512". WikiChip Fuse. 9 December 2019. <a href="https://fuse.wikichip.org/news/3099/centaur-unveils-its-new-server-class-x86-core-cns-adds-avx-512/2/" target="_blank">https://fuse.wikichip.org/news/3099/centaur-unveils-its-new-server-class-x86-core-cns-adds-avx-512/2/</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li> <li id="fn:4"><p>Smith, Ryan (5 November 2021). "VIA To Offload Parts of x86 Subsidiary Centaur to Intel For $125 Million". AnandTech. Retrieved 11 November 2021. <a href="https://www.anandtech.com/show/17049/via-to-offload-parts-of-x86-subsidiary-centaur-to-intel-for-125-million" target="_blank">https://www.anandtech.com/show/17049/via-to-offload-parts-of-x86-subsidiary-centaur-to-intel-for-125-million</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li> <li id="fn:5"><p>Dobberstein, Laura (8 November 2021). "Intel pays VIA $125m to acquire its x86 design talent". The Register. Retrieved 11 November 2021. <a href="https://www.theregister.com/2021/11/08/via_sells_centaur_staff_to_intel/" target="_blank">https://www.theregister.com/2021/11/08/via_sells_centaur_staff_to_intel/</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></p></li> <li id="fn:6"><p>"The Last x86 Via Chip: Unreleased Next-Gen Centaur CNS Saved From Trash Bin, Tested | Tom's Hardware". Tomshardware.com. Retrieved 2022-07-18. <a href="https://www.tomshardware.com/news/last-x86-via-chip-centuar-cns-cpu-tested" target="_blank">https://www.tomshardware.com/news/last-x86-via-chip-centuar-cns-cpu-tested</a> <a href="#fnref:6" class="footnote-back-ref">↩</a></p></li> <li id="fn:7"><p>Besedin, Dmitri. "Detailed Platform Analysis in RightMark Memory Analyzer. Part 12: VIA C7/C7-M Processors". Pricenfees.com. Archived from the original on 2017-02-02. Retrieved 2007-03-12. <a href="https://web.archive.org/web/20170202062644/https://www.pricenfees.com/digit-life-archives/detailed-platform-analysis-rightmark-memory-analyzer-part-12-via-c7c7-m-processors" target="_blank">https://web.archive.org/web/20170202062644/https://www.pricenfees.com/digit-life-archives/detailed-platform-analysis-rightmark-memory-analyzer-part-12-via-c7c7-m-processors</a> <a href="#fnref:7" class="footnote-back-ref">↩</a></p></li> <li id="fn:8"><p>"Centaur Unveils Its New Server-Class x86 Core: CNS; Adds AVX-512". WikiChip Fuse. 9 December 2019. <a href="https://fuse.wikichip.org/news/3099/centaur-unveils-its-new-server-class-x86-core-cns-adds-avx-512/2/" target="_blank">https://fuse.wikichip.org/news/3099/centaur-unveils-its-new-server-class-x86-core-cns-adds-avx-512/2/</a> <a href="#fnref:8" class="footnote-back-ref">↩</a></p></li> <li id="fn:9"><p>Smith, Ryan (5 November 2021). "VIA To Offload Parts of x86 Subsidiary Centaur to Intel For $125 Million". AnandTech. Retrieved 11 November 2021. <a href="https://www.anandtech.com/show/17049/via-to-offload-parts-of-x86-subsidiary-centaur-to-intel-for-125-million" target="_blank">https://www.anandtech.com/show/17049/via-to-offload-parts-of-x86-subsidiary-centaur-to-intel-for-125-million</a> <a href="#fnref:9" class="footnote-back-ref">↩</a></p></li> <li id="fn:10"><p>"The Last x86 Via Chip: Unreleased Next-Gen Centaur CNS Saved From Trash Bin, Tested". TomsHardware. 22 February 2022. <a href="https://www.tomshardware.com/news/last-x86-via-chip-centuar-cns-cpu-tested" target="_blank">https://www.tomshardware.com/news/last-x86-via-chip-centuar-cns-cpu-tested</a> <a href="#fnref:10" class="footnote-back-ref">↩</a></p></li> </ol>