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Negative-bias temperature instability
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<h2 id="physics">Physics</h2> <p>The details of the mechanisms of NBTI have been debated, but two effects are believed to contribute: trapping of positively charged <a href="/facts/Electron_hole/YymdTv9d">holes</a>, and generation of interface states. </p> <ul><li>preexisting traps located in the bulk of the dielectric are filled with holes coming from the channel of pMOS. Those traps can be emptied when the stress voltage is removed, so that the Vth degradation can be recovered over time.</li> <li>interface traps are generated, and these interface states become positively charged when the pMOS device is biased in the "on" state, i.e. with negative gate voltage. Some interface states may become deactivated when the stress is removed, so that the Vth degradation can be recovered over time.</li></ul> <p>The existence of two coexisting mechanisms has resulted in scientific controversy over the relative importance of each component, and over the mechanism of generation and recovery of interface states. </p><p>In sub-micrometer devices <a href="/facts/Nitrogen/Nf1QpGDz">nitrogen</a> is incorporated into the silicon <a href="/facts/Gate_oxide/84kcAbyL">gate oxide</a> to reduce the gate leakage current density and prevent <a href="/facts/Boron/Pmwgd7Mf">boron</a> penetration. It is known that incorporating nitrogen enhances NBTI. For new technologies (45 nm and shorter nominal channel lengths), <a href="/facts/High-%CE%BA/4E8qtXmp">high-κ</a> metal gate stacks are used as an alternative to improve the gate current density for a given equivalent oxide thickness (EOT). Even with the introduction of new materials like <a href="/facts/Hafnium/rBNnlxDS">hafnium</a> oxide in the gate stack, NBTI remains and is often exacerbated by additional charge trapping in the high-κ layer. </p><p>With the introduction of high κ metal gates, a new degradation mechanism has become more important, referred to as PBTI (for positive bias temperature instabilities), which affects nMOS transistor when positively biased. In this case, no interface states are generated and 100% of the Vth degradation may be recovered. </p> <h2 id="see-also">See also</h2> <ul><li><a href="/facts/Hot_carrier_injection/INtYL36b">Hot carrier injection</a></li> <li><a href="/facts/Electromigration/0aEaCFf7">Electromigration</a></li></ul> <ul><li>J.H. Stathis, S. Mahapatra, and T. Grasser, “<i><a href="http://www.iue.tuwien.ac.at/pdf/ib_2018/JB2018_Grasser_1.pdf">Controversial issues in negative bias temperature instability</a></i>”, Microelectronics Reliability, vol 81, pp. 244–251, Feb. 2018. <a href="/facts/Doi_(identifier)/muM9Etpq">doi</a>:<a href="https://doi.org/10.1016%2Fj.microrel.2017.12.035">10.1016/j.microrel.2017.12.035</a></li> <li>T. Grasser et al., “<i>The paradigm shift in understanding the bias temperature instability: From reaction–diffusion to switching oxide traps</i>”, IEEE Transactions on Electron Devices 58 (11), pp. 3652–3666, Nov. 2011. <a href="/facts/Doi_(identifier)/muM9Etpq">doi</a>:<a href="https://doi.org/10.1109%2FTED.2011.2164543">10.1109/TED.2011.2164543</a> <a href="/facts/Bibcode_(identifier)/9HtdQSGB">Bibcode</a>:<a href="https://ui.adsabs.harvard.edu/abs/2011ITED...58.3652G/abstract">2011ITED...58.3652G</a></li> <li>D.K. Schroder, “<i>Negative bias temperature instability: What do we understand?</i>”, Microelectronics Reliability, vol. 47, no. 6, pp. 841–852, June 2007. <a href="/facts/Doi_(identifier)/muM9Etpq">doi</a>:<a href="https://doi.org/10.1016%2Fj.microrel.2006.10.006">10.1016/j.microrel.2006.10.006</a></li> <li>Schroder, Dieter K. (August 2005). <a href="https://www.ewh.ieee.org/r5/denver/sscs/Presentations/2005_08_Schroder.pdf">"Negative Bias Temperature Instability (NBTI): Physics, Materials, Process, and Circuit Issues"</a> (PDF).</li> <li>JH Stathis and <a href="/facts/Sufi_Zafar/w4Y6MTPD">S Zafar</a>, “<i>The negative bias temperature instability in MOS devices: A review</i>”, Microelectronics Reliability, vol 46, no. 2, pp. 278–286, Feb. 2006. <a href="/facts/Doi_(identifier)/muM9Etpq">doi</a>:<a href="https://doi.org/10.1016%2Fj.microrel.2005.08.001">10.1016/j.microrel.2005.08.001</a></li> <li>M. Alam and S. Mahapatra, “<i><a href="https://engineering.purdue.edu/~ee650/downloads/NBTI-Ref1.pdf">A comprehensive model of PMOS NBTI degradation</a></i>”, Microelectronics Reliability, vol. 45, no. 1, pp. 71–81, Jan. 2005. <a href="/facts/Doi_(identifier)/muM9Etpq">doi</a>:<a href="https://doi.org/10.1016%2Fj.microrel.2004.03.019">10.1016/j.microrel.2004.03.019</a></li></ul>