Inter-processor interrupt

<h2 id="mechanism">Mechanism</h2>
<p>The <a href="/facts/OS/360_and_successors/nQbdNbx6">M65MP</a> option of <a href="/facts/OS/360_and_successors/nQbdNbx6">OS/360</a>  used the Direct Control feature of the <a href="/facts/IBM_System/360/7znvpy4K">S/360</a> to generate an interrupt on another processor; on <a href="/facts/IBM_System/370/TRo1jaFw">S/370</a> and its successors, including <a href="/facts/Z/Architecture/FcKYkGn9">z/Architecture</a>, the SIGNAL PROCESSOR instruction provides a more formalized interface. The documentation for some IBM operating systems refers to this as a shoulder tap.
</p><p>On <a href="/facts/IBM_PC_compatible/zGUpl7Sh">IBM PC compatible</a> computers that use the <a href="/facts/Advanced_Programmable_Interrupt_Controller/40lXS8r6">Advanced Programmable Interrupt Controller</a> (APIC), IPI signaling is often performed using the APIC. When a CPU wishes to send an interrupt to another CPU, it stores the <a href="/facts/Interrupt_vector/wq6sxJTo">interrupt vector</a> and the identifier of the target's local APIC in the Interrupt Command Register (ICR) of its own local APIC. A message is then sent via the APIC bus to the target's local APIC, which then issues a corresponding interrupt to its own CPU.
</p>
<h2 id="examples">Examples</h2>
<p>In a multiprocessor system running <a href="/facts/Microsoft_Windows/bwhAhuSL">Microsoft Windows</a>, a processor may interrupt another processor for the following reasons, in addition to the ones listed above:<a class="footnote-ref" id="fnref:3" href="#fn:3"><sup>3</sup></a>
</p>
<ol><li>queue a DISPATCH_LEVEL interrupt to schedule a particular thread for execution;</li>
<li>kernel debugger breakpoint.</li></ol>
<p>IPIs are given an <a href="/facts/IRQL_(Windows)/sFYjdujB">IRQL</a> of 29.<a class="footnote-ref" id="fnref:4" href="#fn:4"><sup>4</sup></a>
</p>
<h2 id="see-also">See also</h2>
<ul><li><a href="/facts/Interrupt/Mm6C4rpc">Interrupt</a></li>
<li><a href="/facts/Interrupt_handler/r9ptAjy7">Interrupt handler</a></li>
<li><a href="/facts/Non-maskable_interrupt/f7CWJU1B">Non-maskable interrupt</a> (NMI)</li></ul>

<h2 id="external-links">External links</h2>
<ul><li><a href="http://linux.linti.unlp.edu.ar/images/0/0c/ULK3-CAPITULO4-UNNOBA.pdf">Interrupts and Exceptions</a></li></ul>

<h2 id="references">References</h2>

<ol>
<li id="fn:1"><p>"Appendix F: Multiprocessing Extensions" (PDF). OS I/O Supervisor Logic - Release 21 - Program Number 360S-CI-505 (PDF). Program Logic. IBM. p. 271. GY28-6616-9. Retrieved August 28, 2022. <a href="http://bitsavers.org/pdf/ibm/360/os/R21.7_Apr73/plm/GY28-6616-9_OS_IO_Superv_PLM_R21.7_Apr73.pdf#page=282" target="_blank">http://bitsavers.org/pdf/ibm/360/os/R21.7_Apr73/plm/GY28-6616-9_OS_IO_Superv_PLM_R21.7_Apr73.pdf#page=282</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li>
<li id="fn:2"><p>"AMD Technical Information Portal". docs.amd.com. Retrieved 2024-07-18. <a href="https://docs.amd.com/r/en-US/am011-versal-acap-trm/Inter-Processor-Interrupts" target="_blank">https://docs.amd.com/r/en-US/am011-versal-acap-trm/Inter-Processor-Interrupts</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li>
<li id="fn:3"><p>"Inter Processor Interrupt usage". Stack Overflow. Retrieved 2024-07-18. <a href="https://stackoverflow.com/questions/15091165/inter-processor-interrupt-usage" target="_blank">https://stackoverflow.com/questions/15091165/inter-processor-interrupt-usage</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li>
<li id="fn:4"><p>Matt (2002-04-28). "Understanding IRQL". Archived from the original on 2019-10-14. Retrieved 2014-12-06. <a href="https://web.archive.org/web/20191014125625/http://ext2fsd.sourceforge.net/documents/irql.htm" target="_blank">https://web.archive.org/web/20191014125625/http://ext2fsd.sourceforge.net/documents/irql.htm</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li>
</ol>

Inter-processor interrupt open-in-new

Inter-processor interrupt