Process corners

<h2 id="significance-to-digital-electronics">Significance to digital electronics</h2>
<p>In <a href="/facts/Very-large-scale_integration/l1Wgqr27">Very-Large-Scale Integration (VLSI)</a> <a href="/facts/Integrated_circuit/fjn6vg7C">integrated circuit</a> <a href="/facts/Microprocessor/Fx9CaQht">microprocessor</a> design and <a href="/facts/Semiconductor_fabrication/Jd23Mu1z">semiconductor fabrication</a>, a process corner represents a three or six <a href="/facts/Standard_deviation/qSug9BRl">sigma variation</a> from <a href="/facts/Nominal_(value)/RS8gq5AC">nominal</a> <a href="/facts/Dopant/DvChmeRL">doping</a> concentrations (and other parameters<a class="footnote-ref" id="fnref:2" href="#fn:2"><sup>2</sup></a>) in transistors on a <a href="/facts/Silicon_wafer/lCBJAoUL">silicon wafer</a>. This variation can cause significant changes in the <a href="/facts/Duty_cycle/B2tbtXTh">duty cycle</a> and <a href="/facts/Slew_rate/Xm5kokVG">slew rate</a> of <a href="/facts/Digital_logic/RHLulvKI">digital</a> signals, and can sometimes result in <a href="/facts/Catastrophic_failure/X5NDNv9r">catastrophic failure</a> of the entire system.
</p><p>Variation may occur for many reasons, such as minor changes in the humidity or temperature in the <a href="/facts/Clean-room/qa97Ff9p">clean-room</a> when wafers are transported, or due to the position of the <a href="/facts/Die_(integrated_circuit)/XWvdlltE">die</a> relative to the center of the wafer.
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<h2 id="types-of-corners">Types of corners</h2>
<p>When working in the schematic domain, we usually only work with <a href="/facts/Front_end_of_line/l1acKMhn">front end of line</a> (FEOL) process corners as these corners will affect the performance of devices. But there is an orthogonal set of process parameters that affect <a href="/facts/Back_end_of_line/881JH4G2">back end of line</a> (BEOL) parasitics.
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<h3>FEOL corners</h3>
<p>One naming convention for process corners is to use two-letter designators, where the first letter refers to the N-channel <a href="/facts/MOSFET/eTDJT2Km">MOSFET</a> (<a href="/facts/NMOS_logic/6hup3T21">NMOS</a>) corner, and the second letter refers to the P channel (<a href="/facts/PMOS_logic/DWmuIrcn">PMOS</a>) corner. In this naming convention, three corners exist: typical, fast and slow. Fast and slow corners exhibit <a href="/facts/Carrier_mobility/aN3bco00">carrier mobilities</a> that are higher and lower than normal, respectively. For example, a corner designated as FS denotes fast NFETs and slow PFETs.
</p><p>There are therefore five possible corners: typical-typical (TT) (not really a corner of an n vs. p mobility graph, but called a corner, anyway), fast-fast (FF), slow-slow (SS), fast-slow (FS), and slow-fast (SF). The first three corners (TT, FF, SS) are called even corners, because both types of devices are affected evenly, and generally do not adversely affect the logical correctness of the circuit. The resulting devices can function at slower or faster clock frequencies, and are often <a href="/facts/Product_binning/BEJrwYMl">binned</a> as such. The last two corners (FS, SF) are called "skewed" corners, and are cause for concern. This is because one type of FET will switch much faster than the other, and this form of imbalanced switching can cause one edge of the output to have much less slew than the other edge. <a href="/facts/Latch_(electronics)/vA99xjM7">Latching</a> devices may then record incorrect values in the logic chain.
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<h3>BEOL corners <a class="footnote-ref" id="fnref:3" href="#fn:3"><sup>3</sup></a></h3>
<p>In addition to the <a href="/facts/FET/TerYC6Nz">FETs</a> themselves, there are more on-chip variation (OCV) effects that manifest themselves at smaller <a href="/facts/Die_shrink/fgJ8nL4b">technology nodes</a>. These include process, voltage and temperature (PVT) variation effects on on-chip interconnect, as well as via structures.
</p><p>Extraction tools often have a nominal corner to reflect the nominal cross section of the process target. Then the corners cbest and cworst were created to model the smallest and largest cross sections that are in the allowed process variation. A simple thought experiment shows that the smallest cross section with the largest vertical spacing will produce the smallest coupling capacitance. CMOS Digital circuits were more sensitive to capacitance than resistance so this variation was initially acceptable. As processes evolved and resistance of wiring became more critical, the additional rcbest and rcworst were created to model the minimum and maximum cross sectional areas for resistance. But the one change is that cross sectional resistance is not dependent on oxide thickness (vertical spacing between wires) so for rcbest the largest is used and for rcworst the smallest is used.
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<h2 id="accounting-for-corners">Accounting for corners</h2>
<p>To combat these variation effects, modern <a href="/facts/90nm/mmjMro9E">technology processes</a> often supply <a href="/facts/SPICE/mIMfxvm7">SPICE</a> or <a href="/facts/BSIM/cLjHW2tm">BSIM</a> <a href="/facts/Simulation/Q4QJV1oI">simulation</a> models for all (or, at the least, TT, FS, and SF) process corners, which enables circuit designers to detect corner <a href="/facts/Skew_lines/2GSpRI8k">skew</a> effects before the design is <a href="/facts/Integrated_circuit_layout/96BnDlT2">laid out</a>, as well as post-layout (through <a href="/facts/Circuit_extraction/zpKAXnuN">parasitics extraction</a>), before it is <a href="/facts/Tapeout/bQ5Fcc9y">taped out</a>.
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<h2 id="external-links">External links</h2>
<ul><li><a href="https://patents.google.com/patent/US6606729">US Patent# 6606729 - Corner simulation methodology</a></li></ul>

<h2 id="references">References</h2>

<ol>
<li id="fn:1"><p>Weste, Neil H.E. & Harris, David (2005). CMOS VLSI Design: A Circuits and Systems Perspective, 3rd Ed. Addison-Wesley, pp.231-235. ISBN 0-321-14901-7. <a href="0-321-14901-7" target="_blank">0-321-14901-7</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li>
<li id="fn:2"><p>Goering, Richard (2005-11-21). "Variability upends designers' plans". EETimes.com. Retrieved 2009-01-22. <a href="http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=174301075" target="_blank">http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=174301075</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li>
<li id="fn:3"><p>"Archived copy". Archived from the original on 2013-09-21. Retrieved 2013-09-20.{{cite web}}:  CS1 maint: archived copy as title (link) <a href="https://web.archive.org/web/20130921053242/http://abelite-da.com/wp-content/uploads/2012/02/C8.png" target="_blank">https://web.archive.org/web/20130921053242/http://abelite-da.com/wp-content/uploads/2012/02/C8.png</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li>
</ol>

Process corners open-in-new

Process corners