Routing (electronic design automation)

<h2 id="types-of-routers">Types of routers</h2>

The earliest types of EDA routers were "manual routers"—the drafter clicked a mouse on the endpoint of each line segment of each net.
Modern PCB design software typically provides "interactive routers"—the drafter selects a pad and clicks a few places to give the EDA tool an idea of where to go, and the EDA tool tries to place wires as close to that path as possible without violating <a href="/facts/Design_rule_checking/GW7N249M">design rule checking</a> (DRC). Some more advanced interactive routers have "push and shove" (aka "shove-aside" or "automoving") features in an interactive router; the EDA tool pushes other nets out of the way, if possible, in order to place a new wire where the drafter wants it and still avoid violating DRC.
Modern PCB design software also typically provides "autorouters" that route all remaining unrouted connections without human intervention.
The main types of autorouters are:

<ul><li><a href="/facts/Maze_router/sm6dnBWB">Maze router</a><a class="footnote-ref" id="fnref:3" href="#fn:3">3</a><a class="footnote-ref" id="fnref:4" href="#fn:4">4</a>
<ul><li>Lee router<a class="footnote-ref" id="fnref:5" href="#fn:5">5</a><a class="footnote-ref" id="fnref:6" href="#fn:6">6</a><a class="footnote-ref" id="fnref:7" href="#fn:7">7</a></li>
<li>Hadlock router<a class="footnote-ref" id="fnref:8" href="#fn:8">8</a></li>
<li>Flood router<a class="footnote-ref" id="fnref:9" href="#fn:9">9</a></li></ul></li>
<li>Line-probe router
<ul><li>Mikami–Tahuchi router<a class="footnote-ref" id="fnref:10" href="#fn:10">10</a></li>
<li>Hightower router<a class="footnote-ref" id="fnref:11" href="#fn:11">11</a><a class="footnote-ref" id="fnref:12" href="#fn:12">12</a><a class="footnote-ref" id="fnref:13" href="#fn:13">13</a><a class="footnote-ref" id="fnref:14" href="#fn:14">14</a></li></ul></li>
<li>Pattern router<a class="footnote-ref" id="fnref:15" href="#fn:15">15</a><a class="footnote-ref" id="fnref:16" href="#fn:16">16</a></li>
<li><a href="/facts/Channel_router/uyKWjlEY">Channel router</a><a class="footnote-ref" id="fnref:17" href="#fn:17">17</a><a class="footnote-ref" id="fnref:18" href="#fn:18">18</a><a class="footnote-ref" id="fnref:19" href="#fn:19">19</a><a class="footnote-ref" id="fnref:20" href="#fn:20">20</a>
<ul><li>Switchbox router<a class="footnote-ref" id="fnref:21" href="#fn:21">21</a></li>
<li>River router<a class="footnote-ref" id="fnref:22" href="#fn:22">22</a></li>
<li>Spine and stitch router<a class="footnote-ref" id="fnref:23" href="#fn:23">23</a></li></ul></li>
<li>Gridless router<a class="footnote-ref" id="fnref:24" href="#fn:24">24</a><a class="footnote-ref" id="fnref:25" href="#fn:25">25</a><a class="footnote-ref" id="fnref:26" href="#fn:26">26</a><a class="footnote-ref" id="fnref:27" href="#fn:27">27</a>
<ul><li>Area router</li>
<li>Graph theory-based router<a class="footnote-ref" id="fnref:28" href="#fn:28">28</a>
<ul><li>Bloodhound router<a class="footnote-ref" id="fnref:29" href="#fn:29">29</a><a class="footnote-ref" id="fnref:30" href="#fn:30">30</a><a class="footnote-ref" id="fnref:31" href="#fn:31">31</a> (<a href="/facts/CADSTAR/UzeJcLcg">CADSTAR</a> by <a href="/facts/Racal-Redac/Xgy5fsyJ">Racal-Redac</a> / <a href="/facts/Zuken/QgM02CaF">Zuken</a>)</li>
<li><a href="/facts/Specctra/0zLshR7q">Specctra</a><a class="footnote-ref" id="fnref:32" href="#fn:32">32</a> (aka <a href="/facts/Allegro_PCB_Router/0zLshR7q">Allegro PCB Router</a>) (gridless since version 10)</li></ul></li>
<li>Topological router
<ul><li><a href="/facts/FreeStyle_Router/RktoDGtg">FreeStyle Router</a> (aka SpeedWay, a <a href="/facts/DOS/sWwDXNmX">DOS</a>-based autorouter for <a href="/facts/P-CAD/nxff1kqF">P-CAD</a>)</li>
<li><a href="/facts/TopoR/RktoDGtg">TopoR</a> (a <a href="/facts/Microsoft_Windows/bwhAhuSL">Windows</a>-based autorouter, also used in <a href="/facts/Eremex/RktoDGtg">Eremex</a>'s Delta Design)</li>
<li><a href="/facts/Toporouter/RktoDGtg">Toporouter</a> (Anthony Blake's open-source router in <a href="/facts/PCB_(software)/bjd89SMa">PCB</a> of the <a href="/facts/GEDA_suite/VJFfLKzu">gEDA suite</a>)</li>
<li><a href="/facts/TopRouter/HqpFxLIE">TopRouter</a> (the topological pre-router in <a href="/facts/CadSoft_Computer/HqpFxLIE">CadSoft</a>/<a href="/facts/Autodesk/6aydGFN5">Autodesk</a>'s <a href="/facts/EAGLE_7.0/HqpFxLIE">EAGLE 7.0</a> and higher)</li>
<li>SimplifyPCB (a topological router with a focus on bundle routing with hand-routing results)<a class="footnote-ref" id="fnref:33" href="#fn:33">33</a></li></ul></li></ul></li></ul>
<h2 id="how-routers-work">How routers work</h2>
Many routers execute the following overall algorithm:

<ul><li>First, determine an approximate course for each net, often by routing on a coarse grid. This step is called global routing,<a class="footnote-ref" id="fnref:34" href="#fn:34">34</a> and may optionally include layer assignment. Global routing limits the size and complexity of the following detailed routing steps, which can be done grid square by grid square.</li></ul>
For detailed routing, the most common technique is rip-up and reroute aka rip-up and retry:<a class="footnote-ref" id="fnref:35" href="#fn:35">35</a>

<ul><li>Select a sequence in which the nets are to be routed.</li>
<li>Route each net in sequence</li>
<li>If not all nets can be successfully routed, apply any of a variety of "cleanup" methods, in which selected routings are removed, the order of the remaining nets to be routed is changed, and the remaining routings are attempted again.</li></ul>
This process repeats until all nets are routed or the program (or user) gives up.
An alternative approach is to treat shorts, design rule violations, obstructions, etc. on a similar footing as excess wire length—that is, as finite costs to be reduced (at first) rather than as absolutes to be avoided. This multi-pass "iterative-improvement" routing method<a class="footnote-ref" id="fnref:36" href="#fn:36">36</a> is described by the following algorithm:

<ul><li>For each of several iterative passes:</li>
<li>Prescribe or adjust the weight parameters of an "objective function" (having a weight parameter value for each unit of excess wire length, and for each type of violation). E.g., for the first pass, excess wire length may typically be given a high cost, while design violations such as shorts, adjacency, etc. are given a low cost. In later passes, the relative ordering of costs is changed so that violations are high-cost, or may be prohibited absolutely.</li>
<li>Select (or randomly choose) a sequence in which nets are to be routed during this pass.</li>
<li>"Rip up" (if previously routed) and reroute each net in turn, so as to minimize the value of the objective function for that net. (Some of the routings will in general have shorts or other design violations.)</li>
<li>Proceed to the next iterative pass until routing is complete and correct, is not further improved, or some other termination criterion is satisfied.</li></ul>
Most routers assign wiring layers to carry predominantly "x" or "y" directional wiring, though there have been routers which avoid or reduce the need for such assignment.<a class="footnote-ref" id="fnref:37" href="#fn:37">37</a> There are advantages and disadvantages to each approach. Restricted directions make power supply design and the control of inter-layer crosstalk easier, but allowing arbitrary routes can reduce the need for vias and decrease the number of required wiring layers.

<h2 id="see-also">See also</h2>
<ul><li><a href="/facts/Electronic_design_automation/o4la3fmX">Electronic design automation</a></li>
<li><a href="/facts/Design_flow_(EDA)/MlaFhpow">Design flow (EDA)</a></li>
<li><a href="/facts/Integrated_circuit_design/sE0qVzyo">Integrated circuit design</a></li>
<li><a href="/facts/Place_and_route/UJgLLNdP">Place and route</a></li>
<li><a href="/facts/Auto_polarity_(differential_pairs)/jusjFQKo">Auto polarity (differential pairs)</a></li>
<li><a href="/facts/Auto_crossover_(Ethernet)/JFKPSq67">Auto crossover (Ethernet)</a></li></ul>

<h2 id="further-reading">Further reading</h2>
<ul><li>Scheffer, Louis K.; Lavagno, Luciano; Martin, Grant (2006). "Chapter 8: Routing". Electronic Design Automation For Integrated Circuits Handbook. Vol. II. Boca Raton, FL, USA: <a href="/facts/CRC_Press/duTuH4hz">CRC Press</a> / <a href="/facts/Taylor_%26_Francis/tLDanRJg">Taylor & Francis</a>. <a href="/facts/ISBN_(identifier)/15AdSPa9">ISBN</a> 978-0-8493-3096-4.</li></ul>
<h2 id="external-links">External links</h2>
<ul><li><a href="http://www.eecs.northwestern.edu/~haizhou/357/lec6.pdf">http://www.eecs.northwestern.edu/~haizhou/357/lec6.pdf</a></li>
<li><a href="http://www.facweb.iitkgp.ernet.in/~isg/CAD/SLIDES/10-grid-routing.pdf">http://www.facweb.iitkgp.ernet.in/~isg/CAD/SLIDES/10-grid-routing.pdf</a></li></ul>

<h2 id="references">References</h2>

<ol>
<li id="fn:1">Garey, M. R.; Johnson, D. S. (1977). "The Rectilinear Steiner Tree Problem is NP-Complete". SIAM Journal on Applied Mathematics. 32 (4): 826–834. doi:10.1137/0132071. ISSN 0036-1399. <a href="http://epubs.siam.org/doi/10.1137/0132071" target="_blank">http://epubs.siam.org/doi/10.1137/0132071</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></li>
<li id="fn:2">Szymanski, Thomas G. (1985). "Dogleg Channel Routing is NP-Complete". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 4 (1): 31–41. doi:10.1109/tcad.1985.1270096. S2CID 17511882. <a href="https://ieeexplore.ieee.org/document/1270096" target="_blank">https://ieeexplore.ieee.org/document/1270096</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></li>
<li id="fn:3">Byers, T. J. (1991-08-01). Printed Circuit Board Design with Microcomputers (1 ed.). New York, USA: Intertext Publications/Multiscience Press, Inc., McGraw-Hill Book Company. pp. 99–101. ISBN 978-0-07-009558-8. LCCN 91-72187. <a href="978-0-07-009558-8" target="_blank">978-0-07-009558-8</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></li>
<li id="fn:4">Ritchey, Lee W. (December 1999). "PCB routers and routing methods" (PDF). PC Design Magazine (February 1999). Speeding Edge. Archived (PDF) from the original on 2018-10-22. Retrieved 2018-10-22. <a href="http://www.speedingedge.com/PDF-Files/pcbrouters.pdf" target="_blank">http://www.speedingedge.com/PDF-Files/pcbrouters.pdf</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></li>
<li id="fn:5">Lee, Chester Y. (September 1961). "An algorithm for path connections and its applications". IRE Transactions on Electronic Computers. EC-10 (3): 346–365. doi:10.1109/TEC.1961.5219222. S2CID 40700386. <a href="/wiki/IRE_Transactions_on_Electronic_Computers" target="_blank">/wiki/IRE_Transactions_on_Electronic_Computers</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></li>
<li id="fn:6">Byers, T. J. (1991-08-01). Printed Circuit Board Design with Microcomputers (1 ed.). New York, USA: Intertext Publications/Multiscience Press, Inc., McGraw-Hill Book Company. pp. 99–101. ISBN 978-0-07-009558-8. LCCN 91-72187. <a href="978-0-07-009558-8" target="_blank">978-0-07-009558-8</a> <a href="#fnref:6" class="footnote-back-ref">↩</a></li>
<li id="fn:7">Kollipara, Ravindranath; Tripathi, Vijai K.; Sergent, Jerry E.; Blackwell, Glenn R.; White, Donald; Staszak, Zbigniew J. (2005). "11.1.3 Packaging Electronic Systems - Design of Printed Wiring Boards" (PDF). In Whitaker, Jerry C.; Dorf, Richard C. (eds.). The Electronics Handbook (2 ed.). CRC Press, Taylor & Francis Group, LLC. p. 1266. ISBN 978-0-8493-1889-4. LCCN 2004057106. Archived (PDF) from the original on 2017-09-25. Retrieved 2017-09-25. <a href="978-0-8493-1889-4" target="_blank">978-0-8493-1889-4</a> <a href="#fnref:7" class="footnote-back-ref">↩</a></li>
<li id="fn:8">Hadlock, Frank O. (1977-12-01). "A shortest path algorithm for grid graphs". Networks. 7 (4): 323–334. doi:10.1002/net.3230070404. <a href="https://www.researchgate.net/publication/227815552" target="_blank">https://www.researchgate.net/publication/227815552</a> <a href="#fnref:8" class="footnote-back-ref">↩</a></li>
<li id="fn:9">Byers, T. J. (1991-08-01). Printed Circuit Board Design with Microcomputers (1 ed.). New York, USA: Intertext Publications/Multiscience Press, Inc., McGraw-Hill Book Company. pp. 99–101. ISBN 978-0-07-009558-8. LCCN 91-72187. <a href="978-0-07-009558-8" target="_blank">978-0-07-009558-8</a> <a href="#fnref:9" class="footnote-back-ref">↩</a></li>
<li id="fn:10">Mikami, Koichi; Tabuchi, Kinya (1968). A computer program for optimal routing of printed circuit connectors. IFIPS Proceedings. Vol. H47. pp. 1745–1478. <a href="/wiki/IFIPS" target="_blank">/wiki/IFIPS</a> <a href="#fnref:10" class="footnote-back-ref">↩</a></li>
<li id="fn:11">Hightower, David W. (1969). "A solution to line-routing problems on the continuous plane". DAC'69: Proceedings of the 6th Annual Conference on Design Automation. ACM Press. pp. 1–24. doi:10.1145/800260.809014. (NB. This contains one of the first descriptions of a "line probe router".) <a href="/wiki/ACM_Press" target="_blank">/wiki/ACM_Press</a> <a href="#fnref:11" class="footnote-back-ref">↩</a></li>
<li id="fn:12">Kollipara, Ravindranath; Tripathi, Vijai K.; Sergent, Jerry E.; Blackwell, Glenn R.; White, Donald; Staszak, Zbigniew J. (2005). "11.1.3 Packaging Electronic Systems - Design of Printed Wiring Boards" (PDF). In Whitaker, Jerry C.; Dorf, Richard C. (eds.). The Electronics Handbook (2 ed.). CRC Press, Taylor & Francis Group, LLC. p. 1266. ISBN 978-0-8493-1889-4. LCCN 2004057106. Archived (PDF) from the original on 2017-09-25. Retrieved 2017-09-25. <a href="978-0-8493-1889-4" target="_blank">978-0-8493-1889-4</a> <a href="#fnref:12" class="footnote-back-ref">↩</a></li>
<li id="fn:13">Minges, Merrill L. (1989). Electronic Materials Handbook: Packaging. Vol. 1. ASM International. ISBN 978-0-87170-285-2. Retrieved 2017-09-27. <a href="978-0-87170-285-2" target="_blank">978-0-87170-285-2</a> <a href="#fnref:13" class="footnote-back-ref">↩</a></li>
<li id="fn:14">Byers, T. J. (1991-08-01). Printed Circuit Board Design with Microcomputers (1 ed.). New York, USA: Intertext Publications/Multiscience Press, Inc., McGraw-Hill Book Company. pp. 99–101. ISBN 978-0-07-009558-8. LCCN 91-72187. <a href="978-0-07-009558-8" target="_blank">978-0-07-009558-8</a> <a href="#fnref:14" class="footnote-back-ref">↩</a></li>
<li id="fn:15">Kollipara, Ravindranath; Tripathi, Vijai K.; Sergent, Jerry E.; Blackwell, Glenn R.; White, Donald; Staszak, Zbigniew J. (2005). "11.1.3 Packaging Electronic Systems - Design of Printed Wiring Boards" (PDF). In Whitaker, Jerry C.; Dorf, Richard C. (eds.). The Electronics Handbook (2 ed.). CRC Press, Taylor & Francis Group, LLC. p. 1266. ISBN 978-0-8493-1889-4. LCCN 2004057106. Archived (PDF) from the original on 2017-09-25. Retrieved 2017-09-25. <a href="978-0-8493-1889-4" target="_blank">978-0-8493-1889-4</a> <a href="#fnref:15" class="footnote-back-ref">↩</a></li>
<li id="fn:16">Minges, Merrill L. (1989). Electronic Materials Handbook: Packaging. Vol. 1. ASM International. ISBN 978-0-87170-285-2. Retrieved 2017-09-27. <a href="978-0-87170-285-2" target="_blank">978-0-87170-285-2</a> <a href="#fnref:16" class="footnote-back-ref">↩</a></li>
<li id="fn:17">Reed, James B.; Sangiovanni-Vincentelli, Alberto; Santamauro, Mauro (1985). "A new symbolic channel router: YACR2". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 4 (3): 203–219. doi:10.1109/TCAD.1985.1270117. S2CID 17065773. [1] <a href="/wiki/IEEE_Transactions_on_Computer-Aided_Design_of_Integrated_Circuits_and_Systems" target="_blank">/wiki/IEEE_Transactions_on_Computer-Aided_Design_of_Integrated_Circuits_and_Systems</a> <a href="#fnref:17" class="footnote-back-ref">↩</a></li>
<li id="fn:18">Minges, Merrill L. (1989). Electronic Materials Handbook: Packaging. Vol. 1. ASM International. ISBN 978-0-87170-285-2. Retrieved 2017-09-27. <a href="978-0-87170-285-2" target="_blank">978-0-87170-285-2</a> <a href="#fnref:18" class="footnote-back-ref">↩</a></li>
<li id="fn:19">Kollipara, Ravindranath; Tripathi, Vijai K.; Sergent, Jerry E.; Blackwell, Glenn R.; White, Donald; Staszak, Zbigniew J. (2005). "11.1.3 Packaging Electronic Systems - Design of Printed Wiring Boards" (PDF). In Whitaker, Jerry C.; Dorf, Richard C. (eds.). The Electronics Handbook (2 ed.). CRC Press, Taylor & Francis Group, LLC. p. 1266. ISBN 978-0-8493-1889-4. LCCN 2004057106. Archived (PDF) from the original on 2017-09-25. Retrieved 2017-09-25. <a href="978-0-8493-1889-4" target="_blank">978-0-8493-1889-4</a> <a href="#fnref:19" class="footnote-back-ref">↩</a></li>
<li id="fn:20">Shankar, Ravi; Fernandez, Eduardo B. (2014-01-12). Einspruch, Norman G. (ed.). VLSI and Computer Architecture. VLSI Electronics Microstructure Science. Vol. 20. Academic Press. ISBN 978-1-48321784-0. Retrieved 2018-10-22. <a href="978-1-48321784-0" target="_blank">978-1-48321784-0</a> <a href="#fnref:20" class="footnote-back-ref">↩</a></li>
<li id="fn:21">Shankar, Ravi; Fernandez, Eduardo B. (2014-01-12). Einspruch, Norman G. (ed.). VLSI and Computer Architecture. VLSI Electronics Microstructure Science. Vol. 20. Academic Press. ISBN 978-1-48321784-0. Retrieved 2018-10-22. <a href="978-1-48321784-0" target="_blank">978-1-48321784-0</a> <a href="#fnref:21" class="footnote-back-ref">↩</a></li>
<li id="fn:22">Shankar, Ravi; Fernandez, Eduardo B. (2014-01-12). Einspruch, Norman G. (ed.). VLSI and Computer Architecture. VLSI Electronics Microstructure Science. Vol. 20. Academic Press. ISBN 978-1-48321784-0. Retrieved 2018-10-22. <a href="978-1-48321784-0" target="_blank">978-1-48321784-0</a> <a href="#fnref:22" class="footnote-back-ref">↩</a></li>
<li id="fn:23">McLellan, Paul (2012-04-23). "Channel Routing Memories". Archived from the original on 2021-05-18. Retrieved 2022-01-01. <a href="https://www.semiwiki.com/forum/content/1208-channel-routing-memories.html" target="_blank">https://www.semiwiki.com/forum/content/1208-channel-routing-memories.html</a> <a href="#fnref:23" class="footnote-back-ref">↩</a></li>
<li id="fn:24">Finch, Alan C.; Mackenzie, Ken J.; Balsdon, G. J.; Symonds, G. (1985-06-23). A Method for Gridless Routing of Printed Circuit Boards (PDF). 22nd ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA. Design Automation Conference, 2009. Dac '09. 46th ACM/IEEE. Newtown, Tewkesbury, Gloucestershire, UK: Racal-Redac Ltd. pp. 509–515. doi:10.1109/DAC.1985.1585990. ISBN 0-8186-0635-5. ISSN 0738-100X. Archived (PDF) from the original on 2018-10-22. Retrieved 2018-10-22. <a href="0-8186-0635-5" target="_blank">0-8186-0635-5</a> <a href="#fnref:24" class="footnote-back-ref">↩</a></li>
<li id="fn:25">Minges, Merrill L. (1989). Electronic Materials Handbook: Packaging. Vol. 1. ASM International. ISBN 978-0-87170-285-2. Retrieved 2017-09-27. <a href="978-0-87170-285-2" target="_blank">978-0-87170-285-2</a> <a href="#fnref:25" class="footnote-back-ref">↩</a></li>
<li id="fn:26">Kollipara, Ravindranath; Tripathi, Vijai K.; Sergent, Jerry E.; Blackwell, Glenn R.; White, Donald; Staszak, Zbigniew J. (2005). "11.1.3 Packaging Electronic Systems - Design of Printed Wiring Boards" (PDF). In Whitaker, Jerry C.; Dorf, Richard C. (eds.). The Electronics Handbook (2 ed.). CRC Press, Taylor & Francis Group, LLC. p. 1266. ISBN 978-0-8493-1889-4. LCCN 2004057106. Archived (PDF) from the original on 2017-09-25. Retrieved 2017-09-25. <a href="978-0-8493-1889-4" target="_blank">978-0-8493-1889-4</a> <a href="#fnref:26" class="footnote-back-ref">↩</a></li>
<li id="fn:27">Webb, Darrell (2012-12-20). "A Tribute to Alan Finch, the Father of Gridless Autorouting". Archived from the original on 2018-10-22. Retrieved 2018-10-22. <a href="https://blog.zuken.com/a-tribute-to-alan-finch-the-father-of-gridless-autorouting/" target="_blank">https://blog.zuken.com/a-tribute-to-alan-finch-the-father-of-gridless-autorouting/</a> <a href="#fnref:27" class="footnote-back-ref">↩</a></li>
<li id="fn:28">Wu, Bo (April 1992). Graph Theory Based Routing Algorithms (PDF) (Thesis). Western Michigan University. S2CID 3357923. Archived from the original (PDF) on 2018-10-22. Retrieved 2018-10-22. <a href="https://web.archive.org/web/20181022112048/https://pdfs.semanticscholar.org/d998/0976dc33c9bfe8b8a049ad8da696526872f7.pdf" target="_blank">https://web.archive.org/web/20181022112048/https://pdfs.semanticscholar.org/d998/0976dc33c9bfe8b8a049ad8da696526872f7.pdf</a> <a href="#fnref:28" class="footnote-back-ref">↩</a></li>
<li id="fn:29">"Computer-Partner Kiel GmbH: "Bloodhound" entflechtet Leiterplatten auf 16 Lagen". Computerwoche (in German). 1992-03-13. Archived from the original on 2018-10-21. Retrieved 2018-10-20. <a href="https://www.computerwoche.de/a/bloodhound-entflechtet-leiterplatten-auf-16-lagen,1133225" target="_blank">https://www.computerwoche.de/a/bloodhound-entflechtet-leiterplatten-auf-16-lagen,1133225</a> <a href="#fnref:29" class="footnote-back-ref">↩</a></li>
<li id="fn:30">Pfeil, Charles (2017-11-02). "A lifetime designing PCBs: From design to software". EDN Network. Archived from the original on 2018-10-21. Retrieved 2018-10-20. <a href="https://www.edn.com/electronics-blogs/all-aboard-/4459033/A-lifetime-designing-PCBs--From-design-to-software" target="_blank">https://www.edn.com/electronics-blogs/all-aboard-/4459033/A-lifetime-designing-PCBs--From-design-to-software</a> <a href="#fnref:30" class="footnote-back-ref">↩</a></li>
<li id="fn:31">Redlich, Detlef. "1.6. Rechnergestützter Leiterplattenentwurf - Entflechtung" (PDF). Schaltungsdesign (in German). Ernst-Abbe-Hochschule Jena (EAH). Archived from the original (PDF) on 2018-10-21. Retrieved 2018-10-20. <a href="https://archive.today/20181021231530/http://web.eah-jena.de/fhj/etit/fb/homepage/home-redlich/lehre/design/Documents/Rechnergest_LP_Entwurf_Einf%C3%BChrung.pdf" target="_blank">https://archive.today/20181021231530/http://web.eah-jena.de/fhj/etit/fb/homepage/home-redlich/lehre/design/Documents/Rechnergest_LP_Entwurf_Einf%C3%BChrung.pdf</a> <a href="#fnref:31" class="footnote-back-ref">↩</a></li>
<li id="fn:32">Redlich, Detlef. "1.6. Rechnergestützter Leiterplattenentwurf - Entflechtung" (PDF). Schaltungsdesign (in German). Ernst-Abbe-Hochschule Jena (EAH). Archived from the original (PDF) on 2018-10-21. Retrieved 2018-10-20. <a href="https://archive.today/20181021231530/http://web.eah-jena.de/fhj/etit/fb/homepage/home-redlich/lehre/design/Documents/Rechnergest_LP_Entwurf_Einf%C3%BChrung.pdf" target="_blank">https://archive.today/20181021231530/http://web.eah-jena.de/fhj/etit/fb/homepage/home-redlich/lehre/design/Documents/Rechnergest_LP_Entwurf_Einf%C3%BChrung.pdf</a> <a href="#fnref:32" class="footnote-back-ref">↩</a></li>
<li id="fn:33">"Simplify Design Automation – the next generation in design methodology". <a href="http://www.simplifyda.com" target="_blank">http://www.simplifyda.com</a> <a href="#fnref:33" class="footnote-back-ref">↩</a></li>
<li id="fn:34">Soukup, Jirí (1979). "Global Router". Proceedings of the 16th Design Automation Conference. San Diego, CA, USA: IEEE Press. pp. 481–489. <a href="http://portal.acm.org/citation.cfm?id=811756" target="_blank">http://portal.acm.org/citation.cfm?id=811756</a> <a href="#fnref:34" class="footnote-back-ref">↩</a></li>
<li id="fn:35">Byers, T. J. (1991-08-01). Printed Circuit Board Design with Microcomputers (1 ed.). New York, USA: Intertext Publications/Multiscience Press, Inc., McGraw-Hill Book Company. pp. 99–101. ISBN 978-0-07-009558-8. LCCN 91-72187. <a href="978-0-07-009558-8" target="_blank">978-0-07-009558-8</a> <a href="#fnref:35" class="footnote-back-ref">↩</a></li>
<li id="fn:36">Rubin, Frank (1974). "An iterative technique for printed wire routing". Proceedings 11th Design Automation Workshop. pp. 308–13. <a href="http://portal.acm.org/citation.cfm?id=811407" target="_blank">http://portal.acm.org/citation.cfm?id=811407</a> <a href="#fnref:36" class="footnote-back-ref">↩</a></li>
<li id="fn:37">Linsker, Ralph (1984). "An iterative-improvement penalty-function-driven wire routing system" (PDF). IBM Journal of Research and Development. 28 (5): 613–624. doi:10.1147/rd.285.0613. <a href="http://www.research.ibm.com/journal/rd/285/ibmrd2805N.pdf" target="_blank">http://www.research.ibm.com/journal/rd/285/ibmrd2805N.pdf</a> <a href="#fnref:37" class="footnote-back-ref">↩</a></li>
</ol>

Routing (electronic design automation) open-in-new

Routing (electronic design automation)