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High-level synthesis
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<h2 id="history">History</h2> <p>Early academic work extracted scheduling, allocation, and binding as the basic steps for high-level-synthesis. Scheduling partitions the algorithm in control steps that are used to define the states in the <a href="/facts/Finite-state_machine/GMusWd0a">finite-state machine</a>. Each control step contains one small section of the algorithm that can be performed in a single clock cycle in the hardware. Allocation and binding maps the instructions and variables to the hardware components, multiplexers, registers and wires of the data path. </p><p>First generation behavioral synthesis was introduced by <a href="/facts/Synopsys/Szv1V36J">Synopsys</a> in 1994 as Behavioral Compiler<a class="footnote-ref" id="fnref:7" href="#fn:7"><sup>7</sup></a> and used <a href="/facts/Verilog/efVqbKXg">Verilog</a> or <a href="/facts/VHDL/H6Exdjfs">VHDL</a> as input languages. The abstraction level used was partially timed (clocked) processes. Tools based on behavioral Verilog or VHDL were not widely adopted in part because neither languages nor the partially timed abstraction were well suited to modeling behavior at a high level. 10 years later, in early 2004, Synopsys <a href="/facts/End-of-life_(product)/LaKyw5RU">end-of-lifed</a> Behavioral Compiler.<a class="footnote-ref" id="fnref:8" href="#fn:8"><sup>8</sup></a> </p><p>In 1998, <a href="/facts/Forte_Design_Systems/Yq1F1rlb">Forte Design Systems</a> introduced its Cynthesizer tool which used SystemC as an entry language instead of Verilog or VHDL. Cynthesizer was adopted by many Japanese companies in 2000 as Japan had a very mature SystemC user community. The first high-level synthesis tapeout was achieved in 2001 by <a href="/facts/Sony/7x4tCtBd">Sony</a> using Cynthesizer. Adoption in the United States started in earnest in 2008. </p><p>In 2006, an efficient and scalable "SDC modulo scheduling" technique was developed on control and data flow graphs <a class="footnote-ref" id="fnref:9" href="#fn:9"><sup>9</sup></a> and was later extended to pipeline scheduling.<a class="footnote-ref" id="fnref:10" href="#fn:10"><sup>10</sup></a> This technique uses the integer linear programming formulation. But it shows that the underlying constraint matrix is <a href="/facts/Unimodular_matrix/J6bRTkN4">totally unimodular</a> (after approximating the resource constraints). Thus, the problem can be solved in polynomial time optimally using a linear programming solver in polynomial time. This work was inducted to the FPGA and Reconfigurable Computing Hall of Fame 2022.<a class="footnote-ref" id="fnref:11" href="#fn:11"><sup>11</sup></a> </p><p>The SDC scheduling algorithm was implemented in the xPilot HLS system<a class="footnote-ref" id="fnref:12" href="#fn:12"><sup>12</sup></a> developed at UCLA,<a class="footnote-ref" id="fnref:13" href="#fn:13"><sup>13</sup></a> and later licensed to the AutoESL Design Technologies, a spin-off from UCLA. AutoESL was acquired by Xilinx (now part of AMD) in 2011,<a class="footnote-ref" id="fnref:14" href="#fn:14"><sup>14</sup></a> and the HLS tool developed by AutoESL became the base of Xilinx HLS solutions, Vivado HLS and Vitis HLS, widely used for FPGA designs. </p> <h2 id="source-input">Source input</h2> <p>The most common source inputs for high-level synthesis are based on standard languages such as <a href="/facts/ANSI_C/rPKeEuPm">ANSI C</a>/<a href="/facts/C%252B%252B/Et0F2qn9">C++</a>, <a href="/facts/SystemC/SEqgs3ka">SystemC</a> and <a href="/facts/MATLAB/qPjLISCk">MATLAB</a>. </p><p>High-level synthesis typically also includes a bit-accurate executable specification as input, since to derive an efficient hardware implementation, additional information is needed on what is an acceptable Mean-Square Error or Bit-Error Rate etc. For example, if the designer starts with an FIR filter written using the "double" floating type, before he can derive an efficient hardware implementation, they need to perform numerical refinement to arrive at a fixed-point implementation. The refinement requires additional information on the level of quantization noise that can be tolerated, the valid input ranges etc. This bit-accurate specification makes the high level synthesis source specification functionally complete.<a class="footnote-ref" id="fnref:15" href="#fn:15"><sup>15</sup></a> Normally the tools infer from the high level code a Finite State Machine and a Datapath that implement arithmetic operations. </p> <h2 id="process-stages">Process stages</h2> <p>The high-level synthesis process consists of a number of activities. Various high-level synthesis tools perform these activities in different orders using different algorithms. Some high-level synthesis tools combine some of these activities or perform them iteratively to converge on the desired solution.<a class="footnote-ref" id="fnref:16" href="#fn:16"><sup>16</sup></a> </p> <ul><li>Lexical processing</li> <li>Algorithm optimization</li> <li>Control/Dataflow analysis</li> <li>Library processing</li> <li>Resource allocation</li> <li>Scheduling</li> <li>Functional unit binding</li> <li>Register binding</li> <li>Output processing</li> <li>Input Rebundling</li></ul> <h2 id="functionality">Functionality</h2> <p>In general, an algorithm can be performed over many clock cycles with few hardware resources, or over fewer clock cycles using a larger number of ALUs, registers and memories. Correspondingly, from one algorithmic description, a variety of hardware microarchitectures can be generated by an HLS compiler according to the directives given to the tool. This is the same trade off of execution speed for hardware complexity as seen when a given program is run on conventional processors of differing performance, yet all running at roughly the same clock frequency. </p> <h3>Architectural constraints</h3> <p>Synthesis constraints for the architecture can automatically be applied based on the design analysis.<a class="footnote-ref" id="fnref:17" href="#fn:17"><sup>17</sup></a> These constraints can be broken into </p> <ul><li>Hierarchy</li> <li>Interface</li> <li>Memory</li> <li>Loop</li> <li>Low-level timing constraints</li> <li>Iteration</li></ul> <h3>Interface synthesis</h3> <p>Interface Synthesis refers to the ability to accept pure C/C++ description as its input, then use automated interface synthesis technology to control the timing and communications protocol on the design interface. This enables interface analysis and exploration of a full range of hardware interface options such as streaming, single- or dual-port RAM plus various handshaking mechanisms. With interface synthesis the designer does not embed interface protocols in the source description. Examples might be: direct connection, one line, 2 line handshake, FIFO.<a class="footnote-ref" id="fnref:18" href="#fn:18"><sup>18</sup></a> </p> <h2 id="vendors">Vendors</h2> <p>Data reported on recent Survey<a class="footnote-ref" id="fnref:19" href="#fn:19"><sup>19</sup></a> </p> <table><tbody><tr><th>Status</th><th><a href="/facts/Compiler/WNfCDFJe">Compiler</a></th><th>Owner</th><th><a href="/facts/Software_license/7enfIqhL">License</a></th><th><a href="/facts/Input%2foutput/WQTE8Jas">Input</a></th><th><a href="/facts/Input%2foutput/WQTE8Jas">Output</a></th><th>Year</th><th>Domain</th><th>Testbench</th><th>FP</th><th>FixP</th></tr><tr><th rowspan="28">In use</th><td><a href="https://www.cadence.com/en_US/home/tools/digital-design-and-signoff/synthesis/stratus-high-level-synthesis.html">Stratus HLS</a></td><td><a href="/facts/Cadence_Design_Systems/6pTzpgFc">Cadence Design Systems</a></td><td><a href="/facts/Commercial_software/WLgyRFMh">Commercial</a></td><td><a href="/facts/C_(programming_language)/Ky2No763">C</a>–<a href="/facts/C%252B%252B/Et0F2qn9">C++</a> <a href="/facts/SystemC/SEqgs3ka">SystemC</a></td><td>RTL</td><td>2015</td><td>All</td><td>Yes</td><td>Yes</td><td>Yes</td></tr><tr><td><a href="http://tima.imag.fr/sls/research-projects/augh/">AUGH</a></td><td>TIMA Lab.</td><td><a href="/facts/Academic_Free_License/kbPBSo3W">Academic</a></td><td>C subset</td><td><a href="/facts/VHDL/H6Exdjfs">VHDL</a></td><td>2012</td><td>All</td><td>Yes</td><td>No</td><td>No</td></tr><tr><td><a href="http://www.yxi.com">eXCite</a> <a href="https://web.archive.org/web/20190917062628/http://www.yxi.com/">Archived</a> 2019-09-17 at the <a href="/facts/Wayback_Machine/nmQ3a6JC">Wayback Machine</a></td><td>Y Explorations</td><td><a href="/facts/Commercial_software/WLgyRFMh">Commercial</a></td><td>C</td><td><a href="/facts/VHDL/H6Exdjfs">VHDL</a>–<a href="/facts/Verilog/efVqbKXg">Verilog</a></td><td>2001</td><td>All</td><td>Yes</td><td>No</td><td>Yes</td></tr><tr><td><a href="http://panda.dei.polimi.it/?page_id=81">Bambu</a></td><td>PoliMi</td><td><a href="/facts/Academic_Free_License/kbPBSo3W">Academic</a></td><td>C</td><td><a href="/facts/VHDL/H6Exdjfs">VHDL</a>–<a href="/facts/Verilog/efVqbKXg">Verilog</a></td><td>2012</td><td>All</td><td>Yes</td><td>Yes</td><td>No</td></tr><tr><td><a href="/facts/Bluespec/INcoF6XJ">Bluespec</a></td><td>BlueSpec, Inc.</td><td><a href="/facts/BSD_licenses/XLtmLp5x">BSD</a>-3</td><td><a href="/facts/Bluespec/INcoF6XJ">Bluespec</a> <a href="/facts/SystemVerilog/wkBdc179">SystemVerilog</a>(<a href="/facts/Haskell/ydEsHuGy">Haskell</a>)</td><td><a href="/facts/SystemVerilog/wkBdc179">SystemVerilog</a></td><td>2007</td><td>All</td><td>No</td><td>No</td><td>No</td></tr><tr><td><a href="https://cacheq.com/">QCC</a></td><td><a href="https://cacheq.com/">CacheQ Systems, Inc.</a></td><td><a href="/facts/Commercial_software/WLgyRFMh">Commercial</a></td><td><a href="/facts/C_(programming_language)/Ky2No763">C</a>, <a href="/facts/C%252B%252B/Et0F2qn9">C++</a>, <a href="/facts/Fortran/m1KqjcMU">Fortran</a></td><td>Host executable + <a href="/facts/Field-programmable_gate_array/M8LSGcAU">FPGA</a> bit file (SystemVerilog is intermediate)</td><td>2018</td><td>All - multi-core and heterogeneous compute</td><td>Yes (C++)</td><td>Yes</td><td>Yes</td></tr><tr><td>CHC</td><td>Altium</td><td><a href="/facts/Commercial_software/WLgyRFMh">Commercial</a></td><td>C subset</td><td><a href="/facts/VHDL/H6Exdjfs">VHDL</a>–<a href="/facts/Verilog/efVqbKXg">Verilog</a></td><td>2008</td><td>All</td><td>No</td><td>Yes</td><td>Yes</td></tr><tr><td>CoDeveloper</td><td>Impulse Accelerated</td><td><a href="/facts/Commercial_software/WLgyRFMh">Commercial</a></td><td>Impulse-C</td><td><a href="/facts/VHDL/H6Exdjfs">VHDL</a></td><td>2003</td><td>Imagestreaming</td><td>Yes</td><td>Yes</td><td>No</td></tr><tr><td><a href="https://www.mathworks.com/products/hdl-coder.html">HDL Coder</a></td><td><a href="/facts/MathWorks/tLCq7ajV">MathWorks</a></td><td><a href="/facts/Commercial_software/WLgyRFMh">Commercial</a></td><td><a href="/facts/MATLAB/qPjLISCk">MATLAB</a>, <a href="/facts/Simulink/H12XCsw9">Simulink</a>, <a href="/facts/Stateflow/Phz8vpAv">Stateflow</a>, Simscape</td><td><a href="/facts/VHDL/H6Exdjfs">VHDL</a>, Verilog</td><td>2003</td><td>Control systems, signal processing, wireless, radar, communications, image and computer vision</td><td>Yes</td><td>Yes</td><td>Yes</td></tr><tr><td><a href="http://www.cyberworkbench.com">CyberWorkBench</a></td><td>NEC</td><td><a href="/facts/Commercial_software/WLgyRFMh">Commercial</a></td><td>C, BDL, <a href="/facts/SystemC/SEqgs3ka">SystemC</a></td><td><a href="/facts/VHDL/H6Exdjfs">VHDL</a>–<a href="/facts/Verilog/efVqbKXg">Verilog</a></td><td>2004</td><td>All</td><td>Cycle,formal</td><td>Yes</td><td>Yes</td></tr><tr><td><a href="https://eda.sw.siemens.com/en-US/ic/catapult-high-level-synthesis">Catapult</a></td><td>Siemens EDA</td><td><a href="/facts/Commercial_software/WLgyRFMh">Commercial</a></td><td><a href="/facts/C_(programming_language)/Ky2No763">C</a>–<a href="/facts/C%252B%252B/Et0F2qn9">C++</a> <a href="/facts/SystemC/SEqgs3ka">SystemC</a></td><td><a href="/facts/VHDL/H6Exdjfs">VHDL</a>–<a href="/facts/Verilog/efVqbKXg">Verilog</a></td><td>2004</td><td>All</td><td>Yes</td><td>Yes</td><td>Yes</td></tr><tr><td>DWARV</td><td>TU. Delft</td><td><a href="/facts/Academic_Free_License/kbPBSo3W">Academic</a></td><td>C subset</td><td><a href="/facts/VHDL/H6Exdjfs">VHDL</a></td><td>2012</td><td>All</td><td>Yes</td><td>Yes</td><td>Yes</td></tr><tr><td><a href="http://www.gaut.fr">GAUT</a></td><td><a href="/facts/University_of_Western_Brittany/xfzQjkj4">University of Western Brittany</a></td><td><a href="/facts/Academic_Free_License/kbPBSo3W">Academic</a></td><td><a href="/facts/C_(programming_language)/Ky2No763">C</a>, <a href="/facts/C%252B%252B/Et0F2qn9">C++</a></td><td><a href="/facts/VHDL/H6Exdjfs">VHDL</a></td><td>2010</td><td>DSP</td><td>Yes</td><td>No</td><td>Yes</td></tr><tr><td><a href="https://hastlayer.com/">Hastlayer</a></td><td>Lombiq Technologies</td><td><a href="/facts/BSD_licenses/XLtmLp5x">BSD</a>-3</td><td><a href="/facts/C_Sharp_(programming_language)/UC2gxeyb">C#</a>, <a href="/facts/C%252B%252B/Et0F2qn9">C++</a>, <a href="/facts/F_Sharp_(programming_language)/jdXHnYz5">F#</a>, ...(<a href="/facts/.NET/PDMQdfFu">.NET</a>)</td><td><a href="/facts/VHDL/H6Exdjfs">VHDL</a></td><td>2015</td><td><a href="/facts/.NET/PDMQdfFu">.NET</a></td><td>Yes</td><td>Yes</td><td>Yes</td></tr><tr><td><a href="http://www.fpga-cores.com/instant-soc/">Instant SoC</a></td><td>FPGA Cores</td><td><a href="/facts/Commercial_software/WLgyRFMh">Commercial</a></td><td><a href="/facts/C_(programming_language)/Ky2No763">C</a>, <a href="/facts/C%252B%252B/Et0F2qn9">C++</a></td><td><a href="/facts/VHDL/H6Exdjfs">VHDL</a>–<a href="/facts/Verilog/efVqbKXg">Verilog</a></td><td>2019</td><td>All</td><td>Yes</td><td>No</td><td>No</td></tr><tr><td><a href="https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/hls-compiler.html">Intel High Level Synthesis Compiler</a></td><td>Intel FPGA (Formerly Altera)</td><td><a href="/facts/Commercial_software/WLgyRFMh">Commercial</a></td><td><a href="/facts/C_(programming_language)/Ky2No763">C</a>, <a href="/facts/C%252B%252B/Et0F2qn9">C++</a></td><td><a href="/facts/Verilog/efVqbKXg">Verilog</a></td><td>2017</td><td>All</td><td>Yes</td><td>Yes</td><td>Yes</td></tr><tr><td><a href="https://www.legupcomputing.com">LegUp HLS</a></td><td>LegUp Computing</td><td><a href="/facts/Commercial_software/WLgyRFMh">Commercial</a></td><td><a href="/facts/C_(programming_language)/Ky2No763">C</a>, <a href="/facts/C%252B%252B/Et0F2qn9">C++</a></td><td><a href="/facts/Verilog/efVqbKXg">Verilog</a></td><td>2015</td><td>All</td><td>Yes</td><td>Yes</td><td>Yes</td></tr><tr><td><a href="http://legup.eecg.utoronto.ca">LegUp</a> <a href="https://web.archive.org/web/20200724081231/http://legup.eecg.utoronto.ca/">Archived</a> 2020-07-24 at the <a href="/facts/Wayback_Machine/nmQ3a6JC">Wayback Machine</a></td><td><a href="/facts/University_of_Toronto/FpGjQNm9">University of Toronto</a></td><td><a href="/facts/Academic_Free_License/kbPBSo3W">Academic</a></td><td>C</td><td><a href="/facts/Verilog/efVqbKXg">Verilog</a></td><td>2010</td><td>All</td><td>Yes</td><td>Yes</td><td>No</td></tr><tr><td>MaxCompiler</td><td>Maxeler</td><td><a href="/facts/Commercial_software/WLgyRFMh">Commercial</a></td><td>MaxJ</td><td>RTL</td><td>2010</td><td><a href="/facts/Data-flow_analysis/jz2oI6sX">Data-flow analysis</a></td><td>No</td><td>Yes</td><td>No</td></tr><tr><td><a href="http://roccc.cs.ucr.edu/">ROCCC</a></td><td>Jacquard Comp.</td><td><a href="/facts/Commercial_software/WLgyRFMh">Commercial</a></td><td>C subset</td><td><a href="/facts/VHDL/H6Exdjfs">VHDL</a></td><td>2010</td><td>Streaming</td><td>No</td><td>Yes</td><td>No</td></tr><tr><td>Symphony C</td><td>Synopsys</td><td><a href="/facts/Commercial_software/WLgyRFMh">Commercial</a></td><td><a href="/facts/C_(programming_language)/Ky2No763">C</a>, <a href="/facts/C%252B%252B/Et0F2qn9">C++</a></td><td><a href="/facts/VHDL/H6Exdjfs">VHDL</a>–<a href="/facts/Verilog/efVqbKXg">Verilog</a>,<a href="/facts/SystemC/SEqgs3ka">SystemC</a></td><td>2010</td><td>All</td><td>Yes</td><td>No</td><td>Yes</td></tr><tr><td><a href="http://www.xilinx.com/products/design-tools/vivado/">VivadoHLS</a>(formerly AutoPilotfrom AutoESL<a class="footnote-ref" id="fnref:20" href="#fn:20"><sup>20</sup></a>)</td><td>Xilinx</td><td><a href="/facts/Commercial_software/WLgyRFMh">Commercial</a></td><td><a href="/facts/C_(programming_language)/Ky2No763">C</a>–<a href="/facts/C%252B%252B/Et0F2qn9">C++</a> <a href="/facts/SystemC/SEqgs3ka">SystemC</a></td><td><a href="/facts/VHDL/H6Exdjfs">VHDL</a>–<a href="/facts/Verilog/efVqbKXg">Verilog</a>,<a href="/facts/SystemC/SEqgs3ka">SystemC</a></td><td>2013</td><td>All</td><td>Yes</td><td>Yes</td><td>Yes</td></tr><tr><td><a href="http://www.cl.cam.ac.uk/research/srg/han/hprls/orangepath/kiwic.html">Kiwi</a></td><td><a href="/facts/University_of_Cambridge/0la7aX9o">University of Cambridge</a></td><td><a href="/facts/Academic_Free_License/kbPBSo3W">Academic</a></td><td>C#</td><td><a href="/facts/Verilog/efVqbKXg">Verilog</a></td><td>2008</td><td><a href="/facts/.NET/PDMQdfFu">.NET</a></td><td>No</td><td>Yes</td><td>Yes</td></tr><tr><td>CHiMPS</td><td><a href="/facts/University_of_Washington/36PG6qkG">University of Washington</a></td><td><a href="/facts/Academic_Free_License/kbPBSo3W">Academic</a></td><td>C</td><td><a href="/facts/VHDL/H6Exdjfs">VHDL</a></td><td>2008</td><td>All</td><td>No</td><td>No</td><td>No</td></tr><tr><td>gcc2verilog</td><td><a href="/facts/Korea_University/oWC8n56E">Korea University</a></td><td><a href="/facts/Academic_Free_License/kbPBSo3W">Academic</a></td><td>C</td><td><a href="/facts/Verilog/efVqbKXg">Verilog</a></td><td>2011</td><td>All</td><td>No</td><td>No</td><td>No</td></tr><tr><td><a href="http://www.nkavvadias.com/hercules/">HercuLeS</a></td><td>Ajax Compilers</td><td><a href="/facts/Commercial_software/WLgyRFMh">Commercial</a></td><td>C/NAC</td><td><a href="/facts/VHDL/H6Exdjfs">VHDL</a></td><td>2012</td><td>All</td><td>Yes</td><td>Yes</td><td>Yes</td></tr><tr><td><a href="https://github.com/etherzhhb/Shang">Shang</a></td><td><a href="/facts/University_of_Illinois_Urbana-Champaign/gusw7HoS">University of Illinois Urbana-Champaign</a></td><td><a href="/facts/Academic_Free_License/kbPBSo3W">Academic</a></td><td>C</td><td><a href="/facts/Verilog/efVqbKXg">Verilog</a></td><td>2013</td><td>All</td><td>Yes</td><td>?</td><td>?</td></tr><tr><td>Trident</td><td>Los Alamos NL</td><td><a href="/facts/Academic_Free_License/kbPBSo3W">Academic</a></td><td>C subset</td><td><a href="/facts/VHDL/H6Exdjfs">VHDL</a></td><td>2007</td><td>Scientific</td><td>No</td><td>Yes</td><td>No</td></tr><tr><th rowspan="11">Aban-doned</th><td>AccelDSP</td><td>Xilinx</td><td><a href="/facts/Commercial_software/WLgyRFMh">Commercial</a></td><td><a href="/facts/MATLAB/qPjLISCk">MATLAB</a></td><td><a href="/facts/VHDL/H6Exdjfs">VHDL</a>–<a href="/facts/Verilog/efVqbKXg">Verilog</a></td><td>2006</td><td>DSP</td><td>Yes</td><td>Yes</td><td>Yes</td></tr><tr><td>C2H</td><td>Altera</td><td><a href="/facts/Commercial_software/WLgyRFMh">Commercial</a></td><td>C</td><td><a href="/facts/VHDL/H6Exdjfs">VHDL</a>–<a href="/facts/Verilog/efVqbKXg">Verilog</a></td><td>2006</td><td>All</td><td>No</td><td>No</td><td>No</td></tr><tr><td>CtoVerilog</td><td><a href="/facts/University_of_Haifa/SHhPqvUI">University of Haifa</a></td><td><a href="/facts/Academic_Free_License/kbPBSo3W">Academic</a></td><td>C</td><td><a href="/facts/Verilog/efVqbKXg">Verilog</a></td><td>2008</td><td>All</td><td>No</td><td>No</td><td>No</td></tr><tr><td>DEFACTO</td><td>University South Cailf.</td><td><a href="/facts/Academic_Free_License/kbPBSo3W">Academic</a></td><td>C</td><td>RTL</td><td>1999</td><td>DSE</td><td>No</td><td>No</td><td>No</td></tr><tr><td>Garp</td><td><a href="/facts/University_of_California%2c_Berkeley/MXVEjklr">University of California, Berkeley</a></td><td><a href="/facts/Academic_Free_License/kbPBSo3W">Academic</a></td><td>C subset</td><td>bitstream</td><td>2000</td><td>Loop</td><td>No</td><td>No</td><td>No</td></tr><tr><td>MATCH</td><td><a href="/facts/Northwest_University_(United_States)/FmfY2j5x">Northwest University</a></td><td><a href="/facts/Academic_Free_License/kbPBSo3W">Academic</a></td><td><a href="/facts/MATLAB/qPjLISCk">MATLAB</a></td><td><a href="/facts/VHDL/H6Exdjfs">VHDL</a></td><td>2000</td><td>Image</td><td>No</td><td>No</td><td>No</td></tr><tr><td>Napa-C</td><td>Sarnoff Corp.</td><td><a href="/facts/Academic_Free_License/kbPBSo3W">Academic</a></td><td>C subset</td><td><a href="/facts/VHDL/H6Exdjfs">VHDL</a>–<a href="/facts/Verilog/efVqbKXg">Verilog</a></td><td>1998</td><td>Loop</td><td>No</td><td>No</td><td>No</td></tr><tr><td>PipeRench</td><td><a href="/facts/Carnegie_Mellon_University/XKd7L2KA">Carnegie Mellon University</a></td><td><a href="/facts/Academic_Free_License/kbPBSo3W">Academic</a></td><td>DIL</td><td>bistream</td><td>2000</td><td>Stream</td><td>No</td><td>No</td><td>No</td></tr><tr><td>SA-C</td><td><a href="/facts/University_of_Colorado/4Vq0nU5H">University of Colorado</a></td><td><a href="/facts/Academic_Free_License/kbPBSo3W">Academic</a></td><td>SA-C</td><td><a href="/facts/VHDL/H6Exdjfs">VHDL</a></td><td>2003</td><td>Image</td><td>No</td><td>No</td><td>No</td></tr><tr><td>SeaCucumber</td><td><a href="/facts/Brigham_Young_University/aYaXLWt2">Brigham Young University</a></td><td><a href="/facts/Academic_Free_License/kbPBSo3W">Academic</a></td><td><a href="/facts/Java_(programming_language)/9ScgFyAL">Java</a></td><td>EDIF</td><td>2002</td><td>All</td><td>No</td><td>Yes</td><td>Yes</td></tr><tr><td>SPARK</td><td><a href="/facts/University_of_California%2c_Irvine/gS3nEt3V">University of California, Irvine</a></td><td><a href="/facts/Academic_Free_License/kbPBSo3W">Academic</a></td><td>C</td><td><a href="/facts/VHDL/H6Exdjfs">VHDL</a></td><td>2003</td><td>Control</td><td>No</td><td>No</td><td>No</td></tr></tbody></table> <ul><li><a href="https://dynamatic.epfl.ch/">Dynamatic</a> from <a href="/facts/%25C3%2589cole_Polytechnique_F%25C3%25A9d%25C3%25A9rale_de_Lausanne/IBPANwjM">EPFL</a>/<a href="/facts/ETH_Zurich/IxHAFGUU">ETH Zurich</a></li> <li><a href="/facts/MATLAB/qPjLISCk">MATLAB</a> HDL Coder <a href="https://www.mathworks.com/products/hdl-coder.html">[1]</a> from <a href="/facts/Mathworks/tLCq7ajV">Mathworks</a><a class="footnote-ref" id="fnref:21" href="#fn:21"><sup>21</sup></a></li> <li>HLS-QSP from CircuitSutra Technologies<a class="footnote-ref" id="fnref:22" href="#fn:22"><sup>22</sup></a></li> <li>C-to-Silicon from <a href="/facts/Cadence_Design_Systems/6pTzpgFc">Cadence Design Systems</a></li> <li>Concurrent Acceleration from Concurrent EDA</li> <li>Symphony C Compiler from <a href="/facts/Synopsys/Szv1V36J">Synopsys</a></li> <li>QuickPlay from PLDA<a class="footnote-ref" id="fnref:23" href="#fn:23"><sup>23</sup></a></li> <li>PowerOpt from ChipVision<a class="footnote-ref" id="fnref:24" href="#fn:24"><sup>24</sup></a></li> <li>Cynthesizer from <a href="/facts/Forte_Design_Systems/Yq1F1rlb">Forte Design Systems</a> (now Stratus HLS from <a href="/facts/Cadence_Design_Systems/6pTzpgFc">Cadence Design Systems</a>)</li> <li><a href="/facts/Catapult_C/stBKgEfz">Catapult C</a> from Calypto Design Systems, part of <a href="/facts/Mentor_Graphics/EAs59CSJ">Mentor Graphics</a> as of 2015, September 16. In November 2016 Siemens announced plans to acquire Mentor Graphics, Mentor Graphics became styled as "Mentor, a Siemens Business". In January 2021, the legal merger of Mentor Graphics with Siemens was completed - merging into the Siemens Industry Software Inc legal entity. Mentor Graphics' name was changed to Siemens EDA, a division of <a href="/facts/Siemens_Digital_Industries_Software/WakFThme">Siemens Digital Industries Software</a>.<a class="footnote-ref" id="fnref:25" href="#fn:25"><sup>25</sup></a></li> <li>PipelineC <a href="https://github.com/JulianKemmerer/PipelineC">[2]</a></li> <li>CyberWorkBench from <a href="/facts/NEC/YnlUsMBA">NEC</a><a class="footnote-ref" id="fnref:26" href="#fn:26"><sup>26</sup></a></li> <li>Mega Hardware <a class="footnote-ref" id="fnref:27" href="#fn:27"><sup>27</sup></a></li> <li>C2R from CebaTech<a class="footnote-ref" id="fnref:28" href="#fn:28"><sup>28</sup></a></li> <li>CoDeveloper from Impulse Accelerated Technologies</li> <li>HercuLeS by Nikolaos Kavvadias<a class="footnote-ref" id="fnref:29" href="#fn:29"><sup>29</sup></a></li> <li>Program In/Code Out (PICO) from Synfora, acquired by Synopsys in June 2010<a class="footnote-ref" id="fnref:30" href="#fn:30"><sup>30</sup></a></li> <li>xPilot from University of California, Los Angeles<a class="footnote-ref" id="fnref:31" href="#fn:31"><sup>31</sup></a></li> <li>Vsyn from vsyn.ru<a class="footnote-ref" id="fnref:32" href="#fn:32"><sup>32</sup></a></li> <li>ngDesign from SynFlow<a class="footnote-ref" id="fnref:33" href="#fn:33"><sup>33</sup></a></li></ul> <h2 id="see-also">See also</h2> <ul><li><a href="/facts/C_to_HDL/G3yWpNhs">C to HDL</a></li> <li><a href="/facts/Electronic_design_automation/o4la3fmX">Electronic design automation</a> (EDA)</li> <li><a href="/facts/Electronic_system-level/vPsKmRR4">Electronic system-level</a> (ESL)</li> <li><a href="/facts/Logic_synthesis/w35wWFfK">Logic synthesis</a></li> <li><a href="/facts/High-level_verification/RaeayMgk">High-level verification</a> (HLV)</li> <li><a href="/facts/SystemVerilog/wkBdc179">SystemVerilog</a></li> <li><a href="/facts/Hardware_acceleration/ej5sM7hB">Hardware acceleration</a></li></ul> <h2 id="further-reading">Further reading</h2> <ul><li>Jason Cong, Jason Lau, Gai Liu, Stephen Neuendorffer, Peichen Pan, Kees Vissers, Zhiru Zhang. FPGA HLS Today: Successes, Challenges, and Opportunities. ACM Transactions on Reconfigurable Technology and Systems, Volume 15, Issue 4, Article No. 5, pp 1–42, December 2022, <a href="https://doi.org/10.1145/3530775">https://doi.org/10.1145/3530775</a>.</li> <li>Michael Fingeroff (2010). <i>High-Level Synthesis Blue Book</i>. Xlibris[<i>self-published source</i>] Corporation. <a href="/facts/ISBN_(identifier)/15AdSPa9">ISBN</a> 978-1-4500-9724-6.</li> <li>Coussy, P.; Gajski, D. D.; Meredith, M.; Takach, A. (2009). "An Introduction to High-Level Synthesis". <i>IEEE Design & Test of Computers</i>. 26 (4): 8–17. <a href="/facts/Doi_(identifier)/muM9Etpq">doi</a>:<a href="https://doi.org/10.1109%2FMDT.2009.69">10.1109/MDT.2009.69</a>. <a href="/facts/S2CID_(identifier)/ldJsHa2Y">S2CID</a> <a href="https://api.semanticscholar.org/CorpusID:52870966">52870966</a>.</li> <li>Ewout S. J. Martens; Georges Gielen (2008). <i>High-level modeling and synthesis of analog integrated systems</i>. Springer. <a href="/facts/ISBN_(identifier)/15AdSPa9">ISBN</a> 978-1-4020-6801-0.</li> <li><a href="/facts/Saraju_Mohanty/sqU8436m">Saraju Mohanty</a>; N. Ranganathan; E. Kougianos & P. Patra (2008). <i>Low-Power High-Level Synthesis for Nanoscale CMOS Circuits</i>. Springer. <a href="/facts/ISBN_(identifier)/15AdSPa9">ISBN</a> 978-0387764733.</li> <li><a href="/facts/Alice_C._Parker/BrjIAeoW">Alice C. Parker</a>; Yosef Tirat-Gefen; Suhrid A. Wadekar (2007). "System-Level Design". In Wai-Kai Chen (ed.). <i>The VLSI handbook</i> (2nd ed.). CRC Press. <a href="/facts/ISBN_(identifier)/15AdSPa9">ISBN</a> 978-0-8493-4199-1. chapter 76.</li> <li>Shahrzad Mirkhani; Zainalabedin Navabi (2007). "System Level Design Languages". In Wai-Kai Chen (ed.). <i>The VLSI handbook</i> (2nd ed.). CRC Press. <a href="/facts/ISBN_(identifier)/15AdSPa9">ISBN</a> 978-0-8493-4199-1. chapter 86. covers the use of C/C++, SystemC, TML and even UML</li> <li>Liming Xiu (2007). <i>VLSI circuit design methodology demystified: a conceptual taxonomy</i>. Wiley-IEEE. <a href="/facts/ISBN_(identifier)/15AdSPa9">ISBN</a> 978-0-470-12742-1.</li> <li>John P. Elliott (1999). <i>Understanding behavioral synthesis: a practical guide to high-level design</i>. Springer. <a href="/facts/ISBN_(identifier)/15AdSPa9">ISBN</a> 978-0-7923-8542-4.</li> <li>Nane, Razvan; Sima, Vlad-Mihai; Pilato, Christian; Choi, Jongsok; Fort, Blair; Canis, Andrew; Chen, Yu Ting; Hsiao, Hsuan; Brown, Stephen; Ferrandi, Fabrizio; Anderson, Jason; Bertels, Koen (2016). "A Survey and Evaluation of FPGA High-Level Synthesis Tools". <i>IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems</i>. 35 (10): 1591–1604. <a href="/facts/Doi_(identifier)/muM9Etpq">doi</a>:<a href="https://doi.org/10.1109%2FTCAD.2015.2513673">10.1109/TCAD.2015.2513673</a>. <a href="/facts/Hdl_(identifier)/rdebSxmC">hdl</a>:<a href="https://hdl.handle.net/11311%2F998432">11311/998432</a>. <a href="/facts/S2CID_(identifier)/ldJsHa2Y">S2CID</a> <a href="https://api.semanticscholar.org/CorpusID:8749577">8749577</a>.</li> <li>Gupta, Rajesh; Brewer, Forrest (2008). "High-Level Synthesis: A Retrospective". <i>"High-level Synthesis: A Retrospective"</i>. Springer. pp. 13–28. <a href="/facts/Doi_(identifier)/muM9Etpq">doi</a>:<a href="https://doi.org/10.1007%2F978-1-4020-8588-8_2">10.1007/978-1-4020-8588-8_2</a>. <a href="/facts/ISBN_(identifier)/15AdSPa9">ISBN</a> 978-1-4020-8587-1.</li></ul> <h2 id="external-links">External links</h2> <ul><li><a href="https://www.youtube.com/watch?v=kgae3Wzqngs&list=PLo7bVbJhQ6qzK6ELKCm8H_WEzzcr5YXHC">Vivado HLS course on Youtube</a></li> <li><a href="http://www.deepchip.com/posts/0480.html">Deepchip Discussion Forum</a></li></ul> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>Coussy, Philippe; Morawiec, Adam, eds. (2008). High-Level Synthesis - Springer. doi:10.1007/978-1-4020-8588-8. ISBN 978-1-4020-8587-1. <a href="978-1-4020-8587-1" target="_blank">978-1-4020-8587-1</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>McFarland, M.C.; Parker, A.C.; Camposano, R. (February 1990). "The high-level synthesis of digital systems". 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