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Instruction unit
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<h2 id="see-also">See also</h2> <ul><li><a href="/facts/Branch_prediction/pGPhFMj5">Branch prediction</a> and the branch prediction buffer <ul><li><a href="/facts/Branch_target_predictor/ImoX6k7L">Branch target predictor</a> and the branch target buffer</li> <li><a href="/facts/Branch_delay_slot/E11U2pF1">Branch delay slot</a></li></ul></li> <li><a href="/facts/Instruction_scheduling/5GuldkLY">Instruction scheduling</a> <ul><li><a href="/facts/Instruction_selection/CqlwPvaa">Instruction selection</a></li> <li><a href="/facts/Data_dependency/pkzwvqCf">Data dependency</a> or <a href="/facts/Data_hazard/hXItYfk1">data hazard</a></li> <li><a href="/facts/Scoreboarding/oAz1Ws6q">Scoreboarding</a></li></ul></li> <li><a href="/facts/Very_long_instruction_word/WJuzewyR">Very long instruction word</a> (VLIW)</li> <li><a href="/facts/Superscalar/gPxRAb25">Superscalar</a> processor</li> <li><a href="/facts/Opcode/UaLMp56C">Opcode</a></li> <li>Analysis of Instruction parallelism, Instruction frequencies, Instruction mix <ul><li><a href="/facts/Instruction_path_length/Wk4jdu67">Instruction path length</a> or Instruction count</li></ul></li></ul> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>Schneck, Paul B. (6 December 2012). Supercomputer Architecture - Paul B. Schneck - Google Książki. Springer. ISBN 9781461579571. <a href="9781461579571" target="_blank">9781461579571</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>John L. Hennessy and David A. Patterson (1990), Computer Architecture: a quantitative approach, Morgan Kaufmann Publishers, Palo Alto, USA, ISBN 1-55860-069-8 <a href="/wiki/John_L._Hennessy" target="_blank">/wiki/John_L._Hennessy</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li> </ol>