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Spacer patterning
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<h2 id="spacer-patterning-without-mandrel-removal">Spacer Patterning Without Mandrel Removal</h2> <p>The mandrel is not removed after the spacer is etched to leave only the sidewall portion, in the case where the mandrel is the <a href="/facts/MOSFET/eTDJT2Km">MOSFET</a> gate stack. The <a href="/facts/Silicon_nitride/58X9QPQJ">silicon nitride</a> sidewall spacer is retained to protect the gate stack and underlying <a href="/facts/Gate_oxide/84kcAbyL">gate oxide</a> during subsequent processing. </p> <h2 id="self-aligned-anti-spacer-double-patterning">Self-Aligned Anti-Spacer Double Patterning</h2> <p>An approach related derived from self-aligned spacer double patterning is so-called "anti-spacer" double patterning. In this approach a first layer coating the mandrel is eventually removed, while a second coated layer over the first layer is planarized and retained. A purely spin-on and wet-processed approached has been demonstrated.<a class="footnote-ref" id="fnref:3" href="#fn:3"><sup>3</sup></a> </p> <h2 id="spacer-is-dielectric-sid">Spacer-Is-Dielectric (SID)</h2> <p>Spacers which define conducting features need to be cut to avoid forming loops. In the alternative spacer-is-dielectric (SID) approach, the spacers define dielectric spaces between conducting features, and so no longer need cuts. The mandrel definition becomes more strategic in the layout, and there is no longer a preference for 1D line-like features. The SID approach has gained popularity due to its flexibility with minimal additional mask exposures.<a class="footnote-ref" id="fnref:4" href="#fn:4"><sup>4</sup></a> The anti-spacer double patterning approach described above naturally fits the SID approach since an additional layer is deposited after the spacer before its removal. </p> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>J. Hwang et al., IEDM 2011, 9.1.1-9.1.4 (2011). <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>BEOL Mask Reduction Using Spacer-Defined Vias and Cuts <a href="https://www.linkedin.com/pulse/beol-mask-reduction-using-spacer-defined-vias-cuts-frederick-chen-zxdhc" target="_blank">https://www.linkedin.com/pulse/beol-mask-reduction-using-spacer-defined-vias-cuts-frederick-chen-zxdhc</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li> <li id="fn:3"><p>M. Hyatt et al., Proc. SPIE 9051, 905118 (2014). <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li> <li id="fn:4"><p>Y. Du et al., "Spacer-Is-Dielectric-Compliant Detailed Routing for Self-Aligned Double Patterning Lithography", DAC 2013. <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li> </ol>