Intelligent verification

<h2 id="history">History</h2>
<p>Achieving confidence that a design is functionally correct continues to become more difficult.  To counter these problems, in the late 1980s fast <a href="/facts/Logic_simulation/er3WT9cg">logic simulators</a> and specialized <a href="/facts/Hardware_description_languages/g19KvKCu">hardware description languages</a> such as <a href="/facts/Verilog/efVqbKXg">Verilog</a> and <a href="/facts/VHDL/H6Exdjfs">VHDL</a> became popular. In the 1990s, constrained random simulation methodologies emerged using <a href="/facts/Hardware_verification_languages/ktV8bQzE">hardware verification languages</a> such as Vera<a class="footnote-ref" id="fnref:1" href="#fn:1"><sup>1</sup></a> and <a href="/facts/E_(verification_language)/hRaWFL4S"><i>e</i></a>, as well as <a href="/facts/SystemVerilog/wkBdc179">SystemVerilog</a> (in 2002), to further improve verification quality and time.
</p><p>Intelligent verification approaches supplement constrained random simulation methodologies, which bases test generation on external input rather than design structure.<a class="footnote-ref" id="fnref:2" href="#fn:2"><sup>2</sup></a>  Intelligent verification is intended to automatically utilize design knowledge during simulation, which has become increasingly important over the last decade due to increased design size and complexity, and a separation between the engineering team that created a design and the team verifying its correct operation.<a class="footnote-ref" id="fnref:3" href="#fn:3"><sup>3</sup></a>  
</p><p>There has been substantial research into the intelligent verification area, and commercial tools that leverage this technique are just beginning to emerge.
</p>
<h2 id="see-also">See also</h2>
<ul><li><a href="/facts/Formal_verification/BYD4GnJR">Formal verification</a></li>
<li><a href="/facts/Functional_verification/8yXmx4aN">Functional verification</a></li></ul>
<h2 id="vendors-offering-intelligent-verification">Vendors offering Intelligent Verification</h2>
<ul><li>Logic Refinery, Inc.</li>
<li><a href="/facts/Mentor_Graphics/EAs59CSJ">Mentor Graphics</a></li>
<li><a href="/facts/Synopsys/Szv1V36J">Synopsys</a> (acquisition of NuSym)</li>
<li>Breker</li>
<li>Springsoft (acquisition of Certess)</li>
<li><a href="http://www.valtrix.in">Valtrix Systems</a></li></ul>
<h2 id="footnotes">Footnotes</h2>

<ul><li>"Mentor offers 'intelligent' testbench generation tool", <i>SDCSource</i>, Feb 18, 2008.</li>
<li><a href="http://www.eetimes.com/news/design/showArticle.jhtml?articleID=207800083">"Nusym focuses on intelligent verification"</a> <i>EETimes</i>, May 2008.</li>
<li>"Lifting the Fog on Intelligent Verification", <i>SCDSource</i>, May 2008.</li></ul>

<h2 id="references">References</h2>

<ol>
<li id="fn:1"><p>"Leveraging Design Insight for Intelligent Verification Methodologies", Embedded, June 2008. <a href="https://archive.today/20130122055042/http://www.embedded.com/columns/technicalinsights/208401632?_requestid=155930" target="_blank">https://archive.today/20130122055042/http://www.embedded.com/columns/technicalinsights/208401632?_requestid=155930</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li>
<li id="fn:2"><p>"Constrained random test struggles to live up to promises" SCDSource, March 2008. <a href="http://www.scdsource.com/article.php?id=137" target="_blank">http://www.scdsource.com/article.php?id=137</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li>
<li id="fn:3"><p>"Leveraging Design Insight for Intelligent Verification Methodologies", Embedded, June 2008. <a href="https://archive.today/20130122055042/http://www.embedded.com/columns/technicalinsights/208401632?_requestid=155930" target="_blank">https://archive.today/20130122055042/http://www.embedded.com/columns/technicalinsights/208401632?_requestid=155930</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li>
</ol>

Intelligent verification open-in-new

Intelligent verification