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Synchronous circuit
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<h2 id="see-also">See also</h2> <ul><li><a href="/facts/Synchronous_network/WX6aSD0m">Synchronous network</a></li> <li><a href="/facts/Asynchronous_circuit/n4ah2j7H">Asynchronous circuit</a></li> <li><a href="/facts/Moore_machine/rVPV8AGH">Moore machine</a></li> <li><a href="/facts/Mealy_machine/Aw1sPMYB">Mealy machine</a></li> <li><a href="/facts/Finite-state_machine/GMusWd0a">Finite-state machine</a></li> <li><a href="/facts/Sequential_logic/Rcs4thlu">Sequential logic</a></li> <li><a href="/facts/Memory_(computing)/hQKVQ51J">Memory</a></li> <li><a href="/facts/Control_unit/8QRX3lwf">Control unit</a></li> <li><a href="/facts/Arithmetic_logic_unit/SgIjPzSc">Arithmetic logic unit</a></li> <li><a href="/facts/Processor_register/32RvbUdz">Processor register</a></li> <li><a href="/facts/Application-specific_integrated_circuit/YGUXpX50">Application-specific integrated circuit</a> (ASIC)</li></ul> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>Asada and Ikeda Laboratories. "Self-synchronous Circuit". "Self Synchronous FPGA". 2009. <a href="http://silicon.u-tokyo.ac.jp/en/research/" target="_blank">http://silicon.u-tokyo.ac.jp/en/research/</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>"self synchronous configurable logic blocks". <a href="https://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=Search_Index_Terms:.QT.self%20synchronous%20configurable%20logic%20blocks.QT.&%20newsearch=partialPref" target="_blank">https://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=Search_Index_Terms:.QT.self%20synchronous%20configurable%20logic%20blocks.QT.&%20newsearch=partialPref</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li> <li id="fn:3"><p>Devlin, Benjamin; Ikeda, Makoto; Asada, Kunihiro. "Energy Minimum Operation with Self Synchronous Gate-Level Autonomous Power Gating and Voltage Scaling". 2012. doi:10.1587/transele.E95.C.546 <a href="http://adsabs.harvard.edu/abs/2012IEITE..95..546D" target="_blank">http://adsabs.harvard.edu/abs/2012IEITE..95..546D</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li> <li id="fn:4"><p>Devlin, B.; Ueki, H.; Mori, S.; Miyauchi, S.; Ikeda, M.; Asada, K. "Performance and side-channel attack analysis of a self synchronous montgomery multiplier processing element for RSA in 40nm CMOS". 2012. doi:10.1109/ASSCC.2012.6570807 <a href="https://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6570807" target="_blank">https://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6570807</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li> </ol>