Streaming SIMD Extensions

<h2 id="registers">Registers</h2>
<p>SSE originally added eight new 128-bit registers known as XMM0 through XMM7. The <a href="/facts/AMD64/cyWvUFlP">AMD64</a> extensions from AMD added a further eight registers XMM8 through XMM15, and this extension is duplicated in the <a href="/facts/Intel_64/cyWvUFlP">Intel 64</a> architecture. There is also a new 32-bit control/status register, MXCSR. The registers XMM8 through XMM15 are accessible only in 64-bit operating mode.
</p>

<p>SSE used only a single data type for XMM registers:
</p>
<ul><li>four 32-bit <a href="/facts/Single-precision/e6Fez7BM">single-precision</a> floating-point numbers</li></ul>
<p><a href="/facts/SSE2/cheNDPSK">SSE2</a> would later expand the usage of the XMM registers to include:
</p>
<ul><li>two 64-bit <a href="/facts/Double-precision/JYyXXYFM">double-precision</a> floating-point numbers or</li>
<li>two 64-bit integers or</li>
<li>four 32-bit integers or</li>
<li>eight 16-bit short integers or</li>
<li>sixteen 8-bit bytes or characters.</li></ul>
<p>Because these 128-bit registers are additional machine states that the <a href="/facts/Operating_system/8XTuvMh2">operating system</a> must preserve across <a href="/facts/Context_switch/N0oJQ6CC">task switches</a>, they are disabled by default until the operating system explicitly enables them. This means that the OS must know how to use the FXSAVE and FXRSTOR instructions, which is the extended pair of instructions that can save all <a href="/facts/X86/Kypq5fgu">x86</a> and SSE register states at once. This support was quickly added to all major IA-32 operating systems.
</p><p>The first CPU to support SSE, the <a href="/facts/Pentium_III/sV1v2Frq">Pentium III</a>, shared execution resources between SSE and the <a href="/facts/Floating-point_unit/XWTW2AbF">floating-point unit</a> (FPU).<a class="footnote-ref" id="fnref:4" href="#fn:4"><sup>4</sup></a> While a <a href="/facts/Compiled/WNfCDFJe">compiled</a> application can interleave FPU and SSE instructions side-by-side, the Pentium III will not issue an FPU and an SSE instruction in the same <a href="/facts/Clock_cycle/9UfTzGHx">clock cycle</a>. This limitation reduces the effectiveness of <a href="/facts/Instruction_pipeline/3zy6CcX1">pipelining</a>, but the separate XMM registers do allow SIMD and scalar floating-point operations to be mixed without the performance hit from explicit MMX/floating-point mode switching.
</p>
<h2 id="sse-instructions">SSE instructions</h2>
<p>SSE introduced both <a href="/facts/Scalar_(computing)/VoCKtwml">scalar</a> and <a href="/facts/Data_structure_alignment/Bqk6zMNS">packed</a> floating-point instructions.
</p>
<h3>Floating-point instructions</h3>
<ul><li>Memory-to-register/register-to-memory/register-to-register data movement
<ul><li>Scalar – MOVSS</li>
<li>Packed – MOVAPS, MOVUPS, MOVLPS, MOVHPS, MOVLHPS, MOVHLPS, MOVMSKPS</li></ul></li>
<li>Arithmetic
<ul><li>Scalar – ADDSS, SUBSS, MULSS, DIVSS, RCPSS, SQRTSS, MAXSS, MINSS, RSQRTSS</li>
<li>Packed – ADDPS, SUBPS, MULPS, DIVPS, RCPPS, SQRTPS, MAXPS, MINPS, RSQRTPS</li></ul></li>
<li><a href="/facts/Comparison_(computer_programming)/nTXrhxN2">Compare</a>
<ul><li>Scalar – CMPSS, COMISS, UCOMISS</li>
<li>Packed – CMPPS</li></ul></li>
<li>Data shuffle and unpacking
<ul><li>Packed – SHUFPS, UNPCKHPS, UNPCKLPS</li></ul></li>
<li><a href="/facts/Type_conversion/FuPD945T">Data-type conversion</a>
<ul><li>Scalar – CVTSI2SS, CVTSS2SI, CVTTSS2SI</li>
<li>Packed – CVTPI2PS, CVTPS2PI, CVTTPS2PI</li></ul></li>
<li><a href="/facts/Bitwise_operation/0gkqnUda">Bitwise</a> logical operations
<ul><li>Packed – ANDPS, ORPS, XORPS, ANDNPS</li></ul></li></ul>
<h3>Integer instructions</h3>
<ul><li>Arithmetic
<ul><li>PMULHUW, PSADBW, PAVGB, PAVGW, PMAXUB, PMINUB, PMAXSW, PMINSW</li></ul></li>
<li>Data movement
<ul><li>PEXTRW, PINSRW</li></ul></li>
<li>Other
<ul><li>PMOVMSKB, PSHUFW</li></ul></li></ul>
<h3>Other instructions</h3>
<ul><li>MXCSR management
<ul><li>LDMXCSR, STMXCSR</li></ul></li>
<li>Cache and Memory management
<ul><li>MOVNTQ, MOVNTPS, MASKMOVQ, PREFETCH0, PREFETCH1, PREFETCH2, PREFETCHNTA, SFENCE</li></ul></li></ul>
<h2 id="example">Example</h2>
<p>The following simple example demonstrates the advantage of using SSE. Consider an operation like vector addition, which is used very often in computer graphics applications. To add two single precision, four-component vectors together using x86 requires four floating-point addition instructions.
</p>
 vec_res.x = v1.x + v2.x;
 vec_res.y = v1.y + v2.y;
 vec_res.z = v1.z + v2.z;
 vec_res.w = v1.w + v2.w;

<p>This corresponds to four x86 FADD instructions in the object code. On the other hand, as the following pseudo-code shows, a single 128-bit 'packed-add' instruction can replace the four scalar addition instructions.
</p>
 movaps xmm0, [v1] ;xmm0 = v1.w | v1.z | v1.y | v1.x 
 addps xmm0, [v2]  ;xmm0 = v1.w+v2.w | v1.z+v2.z | v1.y+v2.y | v1.x+v2.x
 movaps [vec_res], xmm0  ;xmm0

<h2 id="later-versions">Later versions</h2>
<ul><li><a href="/facts/SSE2/cheNDPSK">SSE2</a>, Willamette New Instructions (WNI), introduced with the <a href="/facts/Pentium_4/6tIFuHIF">Pentium 4</a>, is a major enhancement to SSE. SSE2 adds two major features: <a href="/facts/Double-precision/JYyXXYFM">double-precision</a> (64-bit) floating-point for all SSE operations, and MMX integer operations on 128-bit XMM registers. In the original SSE instruction set, conversion to and from integers placed the integer data in the 64-bit MMX registers. SSE2 enables the programmer to perform SIMD math on any data type (from 8-bit integer to 64-bit float) entirely with the XMM vector-register file, without the need to use the legacy MMX or FPU registers. It offers an <a href="/facts/Orthogonal_instruction_set/1eF24vXc">orthogonal set of instructions</a> for dealing with common data types.</li>
<li><a href="/facts/SSE3/Ch9oP4oh">SSE3</a>, also called Prescott New Instructions (PNI), is an incremental upgrade to SSE2, adding a handful of DSP-oriented mathematics instructions and some process (thread) management instructions. It also allowed addition or multiplication of two numbers that are stored in the same register, which wasn't possible in SSE2 and earlier. This capability, known as horizontal in Intel terminology, was the major addition to the SSE3 instruction set. AMD's <a href="/facts/3DNow!/QYJL2HBt">3DNow!</a> extension could do the latter too.</li>
<li><a href="/facts/SSSE3/xlRTcz4I">SSSE3</a>, Merom New Instructions (MNI), is an upgrade to SSE3, adding 16 new instructions which include permuting the bytes in a word, multiplying 16-bit fixed-point numbers with correct rounding, and within-word accumulate instructions. SSSE3 is often mistaken for SSE4 as this term was used during the development of the Core <a href="/facts/Microarchitecture/NFRd4NUL">microarchitecture</a>.</li>
<li><a href="/facts/SSE4/Tnxrl7Ph">SSE4</a>, Penryn New Instructions (PNI), is another major enhancement, adding a <a href="/facts/Dot_product/tNz8MLjT">dot product</a> instruction, additional integer instructions, a <a href="/facts/SSE4/Tnxrl7Ph">popcnt instruction</a> (<a href="/facts/Hamming_weight/dJIW7qg4">Population count</a>: count number of bits set to 1, used extensively e.g. in <a href="/facts/Cryptography/e94PEVau">cryptography</a>), and more.</li>
<li><a href="/facts/XOP_instruction_set/Xey2cAGM">XOP</a>, <a href="/facts/FMA_instruction_set/mqglSHqk">FMA4</a> and <a href="/facts/CVT16_instruction_set/v6G70oa7">CVT16</a> are new iterations announced by <a href="/facts/AMD/CB1G7QTb">AMD</a> in August 2007<a class="footnote-ref" id="fnref:5" href="#fn:5"><sup>5</sup></a><a class="footnote-ref" id="fnref:6" href="#fn:6"><sup>6</sup></a> and revised in May 2009.<a class="footnote-ref" id="fnref:7" href="#fn:7"><sup>7</sup></a></li>
<li><a href="/facts/Advanced_Vector_Extensions/znDpc6Vt">Advanced Vector Extensions</a> (AVX), Gesher New Instructions (GNI), is an advanced version of SSE announced by Intel featuring a widened data path from 128 bits to 256 bits and 3-operand instructions (up from 2). Intel released processors in early 2011 with AVX support.<a class="footnote-ref" id="fnref:8" href="#fn:8"><sup>8</sup></a></li>
<li><a href="/facts/Advanced_Vector_Extensions/znDpc6Vt">AVX2</a> is an expansion of the AVX instruction set.</li>
<li><a href="/facts/AVX-512/2KpGqI8t">AVX-512</a> (3.1 and 3.2) are 512-bit extensions to the 256-bit Advanced Vector Extensions SIMD instructions for x86 instruction set architecture.</li></ul>
<h2 id="identifying">Identifying</h2>
<p>The following programs can be used to determine which, if any, versions of SSE are supported on a system
</p>
<ul><li>Intel Processor Identification Utility<a class="footnote-ref" id="fnref:9" href="#fn:9"><sup>9</sup></a></li>
<li><a href="/facts/CPU-Z/vmpfFkJl">CPU-Z</a> – CPU, motherboard, and memory identification utility.</li>
<li><a href="/facts/Util-linux/vPHnV2Iy">lscpu</a> - provided by the util-linux package in most Linux distributions.</li></ul>
<h2 id="see-also">See also</h2>
<ul><li><a href="/facts/AltiVec/Vn1DY71U">AltiVec</a> - equivalent on <a href="/facts/PowerPC/DqmM9y50">PowerPC</a> architecture</li></ul>

<h2 id="external-links">External links</h2>
<ul><li><a href="https://software.intel.com/sites/landingpage/IntrinsicsGuide/">Intel Intrinsics Guide</a></li></ul>

<h2 id="references">References</h2>

<ol>
<li id="fn:1"><p>"Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 1: Basic Architecture". Intel. April 2022. pp. 5-16–5-19. Archived from the original on April 25, 2022. Retrieved May 16, 2022. <a href="https://cdrdv2.intel.com/v1/dl/getContent/671200" target="_blank">https://cdrdv2.intel.com/v1/dl/getContent/671200</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li>
<li id="fn:2"><p>Diefendorff, Keith (March 8, 1999). "Pentium III = Pentium II + SSE: Internet SSE Architecture Boosts Multimedia Performance" (PDF). Microprocessor Report. 13 (3). Archived (PDF) from the original on April 17, 2018. Retrieved September 1, 2017. <a href="http://docencia.ac.upc.edu/ETSETB/SEGPAR/microprocessors/pentium3%20(mpr).pdf" target="_blank">http://docencia.ac.upc.edu/ETSETB/SEGPAR/microprocessors/pentium3%20(mpr).pdf</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li>
<li id="fn:3"><p>"AMD Extensions to the 3DNow and MMX Instruction Sets Manual" (PDF). Advanced Micro Devices, Inc. March 2000. Archived from the original (PDF) on May 17, 2008. Retrieved April 18, 2024. <a href="https://web.archive.org/web/20080517014932/http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/22466.pdf" target="_blank">https://web.archive.org/web/20080517014932/http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/22466.pdf</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li>
<li id="fn:4"><p>Diefendorff, Keith (March 8, 1999). "Pentium III = Pentium II + SSE: Internet SSE Architecture Boosts Multimedia Performance" (PDF). Microprocessor Report. 13 (3). Archived (PDF) from the original on April 17, 2018. Retrieved September 1, 2017. <a href="http://docencia.ac.upc.edu/ETSETB/SEGPAR/microprocessors/pentium3%20(mpr).pdf" target="_blank">http://docencia.ac.upc.edu/ETSETB/SEGPAR/microprocessors/pentium3%20(mpr).pdf</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li>
<li id="fn:5"><p>Vance, Ashlee (August 3, 2007). "AMD plots single thread boost with x86 extensions". The Register. Archived from the original on April 27, 2011. Retrieved August 24, 2017. <a href="/wiki/Ashlee_Vance" target="_blank">/wiki/Ashlee_Vance</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></p></li>
<li id="fn:6"><p>"AMD64 Technology: 128-Bit SSE5 Instruction Set" (PDF). AMD. August 2007. Archived (PDF) from the original on August 25, 2017. Retrieved August 24, 2017. <a href="http://developer.amd.com/wordpress/media/2012/10/AMD64_128_Bit_SSE5_Instrs.pdf" target="_blank">http://developer.amd.com/wordpress/media/2012/10/AMD64_128_Bit_SSE5_Instrs.pdf</a> <a href="#fnref:6" class="footnote-back-ref">↩</a></p></li>
<li id="fn:7"><p>"AMD64 Technology AMD64 Architecture Programmer's Manual Volume 6: 128-Bit and 256-Bit XOP and FMA4 Instructions" (PDF). AMD. November 2009. Archived (PDF) from the original on January 31, 2017. Retrieved August 24, 2017. <a href="https://support.amd.com/TechDocs/43479.pdf" target="_blank">https://support.amd.com/TechDocs/43479.pdf</a> <a href="#fnref:7" class="footnote-back-ref">↩</a></p></li>
<li id="fn:8"><p>Girkar, Milind (October 1, 2013). "Intel® Advanced Vector Extensions (Intel® AVX)". Intel. Archived from the original on August 25, 2017. Retrieved August 24, 2017. <a href="https://software.intel.com/en-us/isa-extensions/intel-avx" target="_blank">https://software.intel.com/en-us/isa-extensions/intel-avx</a> <a href="#fnref:8" class="footnote-back-ref">↩</a></p></li>
<li id="fn:9"><p>"Download the Intel® Processor Identification Utility". Intel. July 24, 2017. Archived from the original on August 25, 2017. Retrieved August 24, 2017. <a href="https://www.intel.com/content/www/us/en/support/processors/000005651.html" target="_blank">https://www.intel.com/content/www/us/en/support/processors/000005651.html</a> <a href="#fnref:9" class="footnote-back-ref">↩</a></p></li>
</ol>

Streaming SIMD Extensions open-in-new

Streaming SIMD Extensions