SGPIO

<h2 id="history">History</h2>
<p>SGPIO was developed as an engineering collaboration between American Megatrends Inc, at the time makers of back-planes, and LSI-Logic in 2004. SGPIO was later published by the SFF committee as specification <a href="https://doc.xdevs.com/doc/Seagate/SFF-8485.PDF">SFF-8485</a>.
</p>
<h2 id="host-bus-adapters">Host bus adapters</h2>
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<p>The SGPIO signal consists of 4 electrical signals; it typically originates from a <a href="/facts/Host_bus_adapter/nQbbDHF2">host bus adapter</a> (HBA). iPass connectors (Usually SFF-8087 or SFF-8484) carry both SAS/SATA electrical connections between the HBA and the hard drives as well as the 4 SGPIO signals.
</p>

<h2 id="backplanes-with-sgpio-bus-interface">Backplanes with SGPIO bus interface</h2>

<p>A <a href="/facts/Backplane/J6Hwe7Wl">backplane</a> is a circuit board with connectors and power circuitry into which hard drives are attached; they can have multiple slots, each of which can be populated with a hard drive. Typically the back-plane is equipped with <a href="/facts/Light-emitting_diode/gE8x4MDb">LEDs</a> which by their color and activity, indicate the slot's status; typically, a slot's LED will emit a particular color or blink pattern to indicate its current status.
</p>
<h2 id="sgpio-interpretation-and-led-blinking-patterns">SGPIO interpretation and LED blinking patterns</h2>
<p>Although many hardware vendors define their own proprietary LED blinking pattern, the common standard for SGPIO interpretation and LED blinking pattern can be found in the <a href="/facts/IBPI/82bF8PUL">IBPI</a> specification.
</p><p>On back-planes, vendors use typically 2 or 3 LEDs per slot – in both implementations a green LED indicates presence and/or activity – for back-planes with 2 LEDs per slot, the second LED indicates <i>Status</i> whereas in back-planes with 3 LEDs the second and third indicate <i>Locate</i> and <i>Fail</i>.
</p>
<h2 id="electrical-characteristics-of-the-sgpio-bus">Electrical characteristics of the SGPIO bus</h2>
<p>The SGPIO bus consists of 4 signal lines and originates at the HBA, referred to as the <i>initiator</i> and ends at a <a href="/facts/Backplane/J6Hwe7Wl">back-plane</a>, referred to as the <i>target</i>. If a back-plane (or <i>target</i>) is not present the HBA may still drive the bus without any harm to the system; if one does exist, it can communicate back to the HBA using the 4th wire.
</p><p>The SGPIO bus is an <a href="/facts/Open_collector/E12DL8fL">open collector</a> bus with 2.0 kΩ pull-up resistors located at the HBA and the back-plane – as on any open collector bus information is transferred by devices on the bus pulling the lines to <a href="/facts/Ground_(electricity)/F6TEMIVv">ground</a> (GND) using an open collector transistor or open drain <a href="/facts/Field-effect_transistor/TerYC6Nz">FET</a>.
</p>
<h2 id="signal-lines-of-the-sgpio-bus">Signal lines of the SGPIO bus</h2>
<h3>SClock</h3>
<p>The SGPIO bus has a dedicated clock line driven by the initiator (its maximum clock rate is 100 kHz), although many implementations use slower ones (typically 48 kHz).
</p>
<h3>SLoad</h3>
<p>This line is synchronous to the clock and is used to indicate the start of a new frame of data; a new SGPIO frame is indicated by SLoad being high at a rising edge of a clock after having been low for at least 5 clock cycles. The following 4 falling clock edges after a start condition is used to carry a <a href="/facts/4-bit_computing/C0MF1C62">4-bit</a> value from the HBA to the back-plane; the definition of this value is proprietary and varies between system vendors.
</p>
<h3>SDataOut</h3>
<p>This line carries 3 bits of data from the HBA to the backplane: the first bit typically carries <i>activity</i>; the second bit carries <i>locate</i>; and the third bit carries <i>fail</i>. A low value for the first bit indicates <i>no activity</i> and a high value indicates <i>activity</i>.
</p>
<h3>SDataIn</h3>
<p>This line is used by the back-plane and indicates some condition on the back-plane back to the HBA. The first bit being high commonly indicates the presence of a drive. The two following bits are typically unused, and driven low. Because this line would be high for all 3 bits when no backplane is connected, an HBA can detect the presence of a back-plane by the second or third bit of the SDataIn being driven low.
</p><p>The SDataIn and SdataOut then repeats with 3 clocks per drive until the last drive is reached, and the cycle starts over again.
</p>
<h2 id="sgpio-implementation">SGPIO implementation</h2>
<p>There are varieties in how the SGPIO bus is implemented between vendors of HBAs and storage controllers - some vendors will send a continuous stream of data which is advantageous to quickly update the LEDs on a backplane after cables are removed and re-inserted, while others send data only when there is a need to update the LED pattern.
</p>
<h2 id="adoption-of-the-sgpio-specification">Adoption of the SGPIO specification</h2>
<p>SGPIO and the SGPIO spec. is generally adopted and implemented in products from most major HBA and storage controller vendors such as <a href="/facts/LSI_Corporation/6efkIzMM">LSI</a>, <a href="/facts/Intel_Corporation/SMF0gJJX">Intel</a>, <a href="/facts/Adaptec/Ud19UQ2n">Adaptec</a>, <a href="/facts/Nvidia/8QfCgqbu">Nvidia</a>, <a href="/facts/Broadcom/pbh0q7ht">Broadcom</a>, <a href="/facts/Marvell_Technology_Group/IPlIhlj5">Marvell Technology Group</a> and <a href="/facts/PMC-Sierra/acPvuevM">PMC-Sierra</a>. Most products shipping with support for <a href="/facts/Serial_Attached_SCSI/ekU6NmqQ">SAS</a> and <a href="/facts/Serial_ATA/dW8yAMm8">SATA</a> drives support this standard.
</p>
<h2 id="sgpio-timeout-conditions">SGPIO timeout conditions</h2>
<p>The SGPIO spec calls for the target to turn off all indicators when SClock, SLoad and SDataOut have been high for 64 ms; in practice this is not consistently followed by all vendors. Also, in some vendors' implementations the clock may be halted sporadically or stopped during or between cycles. Another – rather impractical – variation between vendors is the state in which the clock is left after a cycle.
</p>
<h2 id="backplane-implementations-of-the-sgpio-bus">Backplane Implementations of the SGPIO bus</h2>
<p>The idea behind this specification was to be able to use low cost <a href="/facts/Complex_programmable_logic_device/CUKHIAID">CPLDs</a> or <a href="/facts/Microcontroller/MKrnAhnm">microcontrollers</a> on a back-plane to drive LEDs; in practice, it has been found that there are variations in timing and interpretations of the bits between vendors, thus a simple CPLD would only work for a specific implementation thoroughly tested with one product from one vendor. A microcontroller is more applicable for this purpose, although the 4-bit SGPIO interface custom bus is not implemented on them – sampling of the 4-bit lines using <a href="/facts/General-purpose_input%2foutput/rIGeu7TW">GPIOs</a> 100 kHz bit operations is too slow for many low-cost microcontrollers to handle whilst handling LED and other functions simultaneously. The length of the bit stream varies between HBA or storage controller; some vendors will stop the bit-stream when reaching the desired drive, while others will clock it all the way through. Some SAS-expander's bit streams may be as long as 108 (36×3) bits.
</p><p>The safest implementation which ensures compatibility between all HBA and storage controller vendors is to use an <a href="/facts/Application-specific_integrated_circuit/YGUXpX50">ASIC</a>, specifically, a combination of a microcontroller core with a hardware SGPIO interface; this concept was patented in 2006 by <a href="/facts/American_Megatrends/1x0ct7aQ">AMI</a> and implemented in a series of backplane controller chips named the MG9071, MG9072, MG9077, and MG9082.
</p><p>These chips will receive 1 or 2 SGPIO streams and drive LEDs accordingly; the latest chip from AMI, the MG9077, can be configured by pull-up and pull-down resistors to adopt to 16 different configurations of SGPIO buses and drive the LEDs accordingly. Since the availability of these chips from AMI, major <a href="/facts/Original_equipment_manufacturer/hmUhIWaS">OEMs</a> including <a href="/facts/NEC/YnlUsMBA">NEC</a>, <a href="/facts/Hitachi%2c_Ltd./KeK38e82">Hitachi</a>, <a href="/facts/Supermicro/oecEUdg1">Supermicro</a>, <a href="/facts/IBM/QszA7nwd">IBM</a>, <a href="/facts/Sun_Microsystems/VJ9EzEFd">Sun Microsystems</a>, and others are using them on their back-planes to receive the SGPIO streams from a variety of HBA vendors and on-board controller chips to consistently drive LEDs with a pre-determined blinking pattern.
</p>
<h2 id="external-links">External links</h2>
<ul><li><a href="https://members.snia.org/document/dl/25923">SFF-8485</a> Specification for Serial GPIO (SGPIO) Bus</li>
<li><a href="https://www.snia.org/sff/specifications">SFF Documents</a> (Documents & Specifications)</li></ul>

SGPIO open-in-new

SGPIO