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Subtractor
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<h2 id="half-subtractor">Half subtractor</h2> <p>The half subtractors can be designed through the combinational Boolean logic circuits [2] as shown in Figure 1 and 2. The half subtractor is a <a href="/facts/Logic_circuit/RHLulvKI">combinational circuit</a> which is used to perform subtraction of two bits. It has two inputs, the <a href="/facts/Minuend/dEUrp6k0">minuend</a> X {\displaystyle X} and <a href="/facts/Subtrahend/dEUrp6k0">subtrahend</a> Y {\displaystyle Y} and two outputs the difference D {\displaystyle D} and borrow out B out {\displaystyle B_{\text{out}}} . The borrow out signal is set when the subtractor needs to borrow from the next digit in a multi-digit subtraction. That is, B out = 1 {\displaystyle B_{\text{out}}=1} when X < Y {\displaystyle X<Y} . Since X {\displaystyle X} and Y {\displaystyle Y} are bits, B out = 1 {\displaystyle B_{\text{out}}=1} if and only if X = 0 {\displaystyle X=0} and Y = 1 {\displaystyle Y=1} . An important point worth mentioning is that the half subtractor diagram aside implements X − Y {\displaystyle X-Y} and not Y − X {\displaystyle Y-X} since B out {\displaystyle B_{\text{out}}} on the diagram is given by </p> B out = X ¯ ⋅ Y {\displaystyle B_{\text{out}}={\overline {X}}\cdot Y} . <p>This is an important distinction to make since subtraction itself is not <a href="/facts/Commutative/WaYxJLxd">commutative</a>, but the difference bit D {\displaystyle D} is calculated using an <a href="/facts/XOR_gate/WSfdqTcA">XOR gate</a> which is commutative. </p> <p>The <a href="/facts/Truth_table/4KsmArDW">truth table</a> for the half subtractor is: </p> <table><tbody><tr><th colspan="2">Inputs</th><th colspan="2">Outputs</th></tr><tr><th><i>X</i></th><th><i>Y</i></th><th><i>D</i></th><th><i>B</i>out</th></tr><tr><td>0</td><td>0</td><td>0</td><td>0</td></tr><tr><td>0</td><td>1</td><td>1</td><td>1</td></tr><tr><td>1</td><td>0</td><td>1</td><td>0</td></tr><tr><td>1</td><td>1</td><td>0</td><td>0</td></tr></tbody></table> <p>Using the table above and a <a href="/facts/Karnaugh_map/saFd8oNl">Karnaugh map</a>, we find the following logic equations for D {\displaystyle D} and B out {\displaystyle B_{\text{out}}} : </p> D = X ⊕ Y {\displaystyle D=X\oplus Y} B out = X ¯ ⋅ Y {\displaystyle B_{\text{out}}={\overline {X}}\cdot Y} . <p>Consequently, a simplified half-subtract circuit, advantageously avoiding crossed traces in particular as well as a negate gate is: </p> X ── XOR ─┬─────── |X-Y|, is 0 if X equals Y, 1 otherwise ┌──┘ └──┐ Y ─┴─────── AND ── borrow, is 1 if Y > X, 0 otherwise <p>where lines to the right are outputs and others (from the top, bottom or left) are inputs. </p> <h2 id="full-subtractor">Full subtractor</h2> <p>The full subtractor is a <a href="/facts/Logic_circuit/RHLulvKI">combinational circuit</a> which is used to perform subtraction of three input <a href="/facts/Bit/S972NSaD">bits</a>: the minuend X {\displaystyle X} , subtrahend Y {\displaystyle Y} , and borrow in B in {\displaystyle B_{\text{in}}} . The full subtractor generates two output bits: the difference D {\displaystyle D} and borrow out B out {\displaystyle B_{\text{out}}} . B in {\displaystyle B_{\text{in}}} is set when the previous digit is borrowed from X {\displaystyle X} . Thus, B in {\displaystyle B_{\text{in}}} is also subtracted from X {\displaystyle X} as well as the subtrahend Y {\displaystyle Y} . Or in symbols: X − Y − B in {\displaystyle X-Y-B_{\text{in}}} . Like the half subtractor, the full subtractor generates a borrow out when it needs to borrow from the next digit. Since we are subtracting Y {\displaystyle Y} and B in {\displaystyle B_{\text{in}}} from X {\displaystyle X} , a borrow out needs to be generated when X < Y + B in {\displaystyle X<Y+B_{\text{in}}} . When a borrow out is generated, 2 is added in the current digit. (This is similar to the subtraction algorithm in decimal. Instead of adding 2, we add 10 when we borrow.) Therefore, D = X − Y − B in + 2 B out {\displaystyle D=X-Y-B_{\text{in}}+2B_{\text{out}}} . </p> <p>The truth table for the full subtractor is: </p> <table><tbody><tr><th colspan="3">Inputs</th><th colspan="2">Outputs</th></tr><tr><th><i>X</i></th><th><i>Y</i></th><th><i>B</i>in</th><th><i>D</i></th><th><i>B</i>out</th></tr><tr><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr><tr><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td></tr><tr><td>0</td><td>1</td><td>0</td><td>1</td><td>1</td></tr><tr><td>0</td><td>1</td><td>1</td><td>0</td><td>1</td></tr><tr><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td></tr><tr><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td></tr><tr><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td></tr><tr><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td></tr></tbody></table> <p>Therefore the equation is: </p><p> D = X ⊕ Y ⊕ B i n {\displaystyle D=X\oplus Y\oplus B_{in}} </p><p> B o u t = X ¯ B i n + X ¯ Y + Y B i n {\displaystyle B_{out}={\bar {X}}B_{in}+{\bar {X}}Y+YB_{in}} </p> <h2 id="see-also">See also</h2> <ul><li><a href="/facts/Adder_(electronics)/Bc81gxBD">Adder (electronics)</a></li> <li><a href="/facts/Carry-lookahead_adder/tqVWGB7d">Carry-lookahead adder</a></li> <li><a href="/facts/Carry-save_adder/QGT9AqMd">Carry-save adder</a></li> <li><a href="/facts/Adding_machine/oyHBLrrs">Adding machine</a></li> <li><a href="/facts/Adder-subtractor/4PUoE3cw">Adder-subtractor</a></li></ul> <ol><li>Foundations Of Digital Electronics by Elijah Mwangi</li> <li>Beltran, A.A., Nones, K., Salanguit, R.L., Santos, J.B., Santos, J.M., & Dizon, K.J. (2021). <a href="https://www.semanticscholar.org/paper/Low-Power-NAND-Gate%E2%80%93based-Half-and-Full-Adder-Using-Beltran-Nones/8aeca4f742da6dbfc19fcccb98dea322bee2a895">Low Power NAND Gate–based Half and Full Adder / Subtractor Using CMOS Technique.</a></li></ol> <h2 id="external-links">External links</h2> <ul><li><a href="http://www.fullchipdesign.com/binary_adder_subtractor.htm">N bit Binary addition or subtraction using single circuit.</a></li></ul>